Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
xxxii Freescale Semiconductor
Information in this book is subject to change without notice, as described in the disclaimers on the
title page of this book. As with any technical documentation, it is the readers’ responsibility to be
sure they are using the most recent version of the documentation.
Audience
It is assumed that the reader understands operating systems, microprocessor system design, and
the basic principles of RISC processing.
Organization
Following is a summary and a brief description of the major sections of this manual:
• Chapter 1, “Core Complex Overview,” provides a general description of e500
functionality.
• Chapter 2, “Register Model,” is useful for software engineers who need to understand the
programming model for the three programming environments and the functionality of each
register.
• Chapter 3, “Instruction Model,” provides an overview of the addressing modes and a
description of the instructions. Instructions are organized by function.
• Chapter 4, “Execution Timing,” describes how instructions are fetched, decoded, issues,
executed, and completed and how instruction results are presented to the processor and
memory system. Tables are provided that indicate latency and throughput for each of the
instructions supported by the e500.
• Chapter 5, “Interrupts and Exceptions,” describes how the e500 implements the interrupt
model as it is defined by the Book E architecture.
• Chapter 6, “Power Management,” describes the power management facilities as they are
defined by Book E and implemented in the e500 core.
• Chapter 7, “Performance Monitor,” describes the e500 implementation of the performance
monitor APU that is defined by the Freescale Book E implementation standards.
• Chapter 8, “Debug Support,” describes the debug facilities as they are defined by Book E
and implemented in the e500 core.
• Chapter 9, “Timer Facilities,” describes the Book E-defined timer facilities implemented in
the e500 core. These resources include the time base (TB), decrementer (DEC),
fixed-interval timer (FIT), and watchdog timer.
• Chapter 10, “Auxiliary Processing Units (APUs),” lists the extensions to the
Book E–defined programming model that are supported on the e500 and describes the
e500-specific branch target buffer locking APU.
• Chapter 11, “L1 Caches,” provides specific hardware and software details regarding the
e500 cache implementation.