Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
1-28 Freescale Semiconductor
Core Complex Overview
(RPN), the user attribute bits (U0–U3), and permission bits (UX, SX, UW, SW, UR, SR) that
specify user and supervisor read, write, and execute permissions.
The e500 does not implement MAS5.
MAS registers are affected by the following instructions (see Section 12.4, “TLB
Instructions—Implementation ,” for more detailed information):
• MAS registers are accessed with the mtspr and mfspr instructions.
• The TLB Read Entry instruction (tlbre) causes the contents of a single TLB entry from the
L2 MMU to be placed in defined locations in MAS0–MAS3 (and optionally MAS7 on the
e500v2). The TLB entry to be extracted is determined by information written to MAS0 and
MAS2 before the tlbre instruction is executed.
• The TLB Write Entry instruction (tlbwe) causes the information stored in certain locations
of MAS0–MAS3 (and MAS7 on the e500v2) to be written to the TLB specified in MAS0.
• The TLB Search Indexed instruction (tlbsx) updates MAS registers conditionally, based on
success or failure of a lookup in the L2 MMU. The lookup is specified by the instruction
encoding and specific search fields in MAS6. The values placed in the MAS registers may
differ, depending on a successful or unsuccessful search.
For TLB miss and certain MMU-related DSI/ISI exceptions, MAS4 provides default values for
updating MAS0–MAS2.
1.9.3 Process ID Registers (PID0–PID2)
The e500 core complex also implements three process ID (PID) registers that hold the values used
to construct the three virtual addresses for each access. These process IDs provide an extended
page sharing capability. Which of these three virtual addresses is used is controlled by the TID
field of a matching TLB entry, and when TID = 0x00 (identifying a page as globally shared), the
PID values are ignored.
A hit to multiple TLB entries in the L1 MMU (even if they are in separate arrays) or a hit to
multiple entries in the L2 MMU is considered to be a programming error.
1.9.4 TLB Coherency
The core complex provides the ability to invalidate a TLB entry, as defined in the Book E
architecture. The tlbivax instruction invalidates a matching local TLB entry. Execution of this
instruction is also broadcast on the core complex bus (CCB) if HID1[ABE] is set. The core
complex also snoops TLB invalidate transactions on the CCB from other bus masters.