Freescale Semiconductor PowerPC e500 Core, Reference Manual

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PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor Part II-1
Part II
e500 Core Complex
This part describes the features of the e500 core complex that comprise its memory subsystem and
auxiliary features. It contains the following chapters:
• Chapter 9, “Timer Facilities ,” describes the Book E-defined timer facilities implemented in
the e500 core. These resources include the time base (TB), decrementer (DEC),
fixed-interval timer (FIT), and watchdog timer.
• Chapter 10, “Auxiliary Processing Units (APUs) ,” describes APUs implemented on the
e500, such as the isel instruction, performance monitor, signal processing engine, branch
target buffer (BTB) locking, cache block lock and unlock, and machine check APUs.
• Chapter 11, “L1 Caches ,” describes the organization of the on-chip level-one instruction
and data caches, cache coherency protocols, cache control instructions, and various cache
operations. It describes the interaction that occurs in the memory subsystem, which consists
of the memory management unit (MMU), caches, load/store unit (LSU), and core complex
bus (CCB). The chapter also describes the replacement algorithms used for each of the L1
caches.
• Chapter 12, “Memory Management Units ,” describes the implementation details of the
e500 core complex MMU relative to the Book E architecture and the Motorola Book E
standards.
• Chapter 13, “Core Complex Bus (CCB),” describes those aspects of the CCB that are
configurable or that provide status information through the programming interface. It
provides a glossary of those signals that are mentioned in other chapters to offer a clearer
understanding of how the core is integrated as part of a larger device.