Freescale Semiconductor PowerPC e500 Core, Reference Manual

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Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-7
• The issue stage reads source operands from rename registers and register files and
determines when instructions are latched into reservation stations.
The general behavior of the two issue queues is described as follows:
— The GIQ accepts as many as two instructions from the dispatch unit per cycle. SU1,
SU2, MU, and all LSU instructions (including SPE APU loads and stores) are
dispatched to the GIQ, shown in
Figure 4-3 .
Figure 4-3. GPR Issue Queue (GIQ)
Instructions can be issued out-of-order from GIQ1–GIQ0. GIQ0 can issue to SU1, MU,
and LSU. GIQ1 can issue to SU2, MU, and LSU.
SU2 executes a subset of the instructions that can be executed in SU1. The ability to
identify and dispatch instructions to SU2 increases the availability of SU1 to execute
more computationally intensive instructions.
An instruction in GIQ1 destined for SU2 or the LSU need not wait for an MU
instruction in GIQ0 that is stalled behind a long-latency divide.
• The execute stage is comprised of individual non-blocking execution units implemented in
parallel. Each execution unit has a reservation station that must be available for an
instruction issue to occur. In most cases, instructions are issued both to the reservation
station and to the execution unit simultaneously. However, under some circumstances, an
instruction may issue only to a reservation station.
In this stage, operands assigned to the execution stage are latched.
The e500 has the following execution units:
— Branch unit (BU)—executes branches and CR logical operations
— Load/store unit (LSU)—executes loads from and stores to memory, as well as some
MMU control, cache control, and cache locking instructions. This includes byte,
half-word, and word instructions defined by the PowerPC architecture and 64-bit load
and store instructions defined as part of the SPE APU. The load/store queues are
described in
Section 4.4.2.1, “Load/Store Unit Queueing Structures .”
— Two simple units (SU1 and SU2)—execute move to/from SPR instructions, logical
instructions, and all computational instructions except multiply and divide instructions.
These execution units also execute all vector and scalar computational instructions
GIQ1
GIQ3
GIQ0
GIQ2
To SU2, MU, or LSU
From IQ0/IQ1
To SU1, MU, or LSU