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User’s Manual U14359EJ4V0UM
CHAPTER 4 BUS CONTROL FUNCTION
The V850E/MA1 is provided with an external bus interface function by which external I/O and memories, such as
ROM and RAM, can be connected.
4.1
Features
• 16-bit/8-bit data bus sizing function
• 8-space chip select function
• Wait function
• Programmable wait function, through which up to 7 wait states can be inserted for each memory block
• External wait function via WAIT pin
• Idle state insertion function
• Bus mastership arbitration function
• Bus hold function
• External device connection enabled via bus control/port alternate function pins
4.2
Bus Control Pins
The following pins are used for connection to external devices.
Bus Control Pin (Function When in Control Mode)
Function When in Port Mode
Register for Port/Control
Mode Switching
Data bus (D0 to D15)
PDL0 to PDL15 (Port DL)
PMCDL
Address bus (A0 to A15)
PAL0 to PAL15 (Port AL)
PMCAL
Address bus (A16 to A25)
PAH0 to PAH9 (Port AH)
PMCAH
Chip select (CS0 to SC7, RAS1, RAS3, RAS4, RAS6,
IOWR, IORD)
PCS0 to PCS7 (Port CS)
PMCCS
SDRAM sync control (SDCKE, SDCLK)
PCD0, PCD1 (Port CD)
Byte access control/SDRAM control (LBE/SDCAS,
UBE/SDRAS)
PCD2, PCD3 (Port CD)
PMCCD
Read/write control (LCAS/LWR/LDQM, UCAS/UWR/UDQM,
RD, WE, OE)
PCT0, PCT1, PCT4 to PCT6
(Port CT)
Bus cycle start (BCYST)
PCT7 (Port CT)
PMCCT
External wait control (WAIT)
PCM0 (Port CM)
Internal system clock (CLKOUT)
PCM1 (Port CM)
Bus hold control (HLDRQ, HLDAK)
PCM2, PCM3 (Port CM)
DRAM refresh control (REFRQ)
PCM4 (Port CM)
Self-refresh control (SELFREF)
PCM5 (Port CM)
PMCCM
Remark
In the case of single-chip mode 1 and ROMless modes 0 and 1, when the system is reset, each bus
control pin becomes unconditionally valid. (However, D8 to D15 are valid only in single-chip mode 1
and ROMless mode 0.)
