CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
User’s Manual U14359EJ4V0UM
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(b) Setting these registers as compare registers (CMSn0 and CMSn1 of TMCCn1 = 1)
When these registers are set as compare registers, the TMCn and register values are compared for each
count clock, and an interrupt is generated by a match. If the CCLRn bit of timer mode control register
Cn1 (TMCCn1) is set (1), the TMCn value is cleared (0) at the same time as a match with the CCCn0
register (it is not cleared (0) by a match with the CCCn1 register) (n = 0 to 3).
A compare register is equipped with a set/reset function. The corresponding timer output (TO0n) is set or
reset, in synchronization with the generation of a match signal (n = 0 to 3).
The interrupt selection source differs according to the function of the selected register.
Cautions 1. To write to capture/compare registers Cn0 and Cn1, always set the TMCCAEn bit to
1 first. If the TMCCAEn bit is 0, the data that is written will be invalid.
2. Write to capture/compare registers Cn0 and Cn1 after setting them as compare
registers via TMCCn0 and TMCCn1 register settings. If they are set as capture
registers (CMSn0 and CMSn1 bits of TMCCn1 register = 0), no data is written even if
a write operation is performed to CCCn0 and CCCn1.
3. When these registers are set as compare registers, INTP0n0 and INTP0n1 cannot be
used (n = 0 to 3).
