CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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(2) SDRAM single write cycle
The SDRAM single write cycle is a cycle for writing to SDRAM by executing a write instruction (ST) for the
SDRAM area or by 2-cycle DMA transfer.
In the SDRAM single write cycle, the active command (ACT) and write command (WR) are issued for
SDRAM in that order. During on-page access, however, only the write command is issued and the precharge
command and active command are not issued. When a page change occurs in the same bank, the
precharge command (PR) is issued before the active command.
A one-state TW cycle is always inserted immediately before every write command, which is activated by the
CPU.
The timing charts of the SDRAM single write cycle are shown below.
