7
User’s Manual U14359EJ4V0UM
Major Revisions in This Edition (2/3)
Page
Description
p.282
Addition of Caution to and deletion of reserved word < > of device file from
7.3.5 Interrupt mask registers
0 to 3 (IMR0 to IMR3)
p.284
Addition of Caution to
7.3.9 (1) External interrupt mode registers 1 to 4 (INTM1 to INTM4)
p.286
Addition of Caution to
7.3.9 (2) Valid edge select registers C0 to C3 (SESC0 to SESC3)
p.297
Change of description in
Figure 7-14 Pipeline Operation at Interrupt Request Acknowledgement
(Outline)
p.298
Change of description in
7.8 Periods in Which Interrupts Are Not Acknowledged
p.316
Addition of description to
9.5.4 (2) (a) Release according to a non-maskable interrupt request or an
unmasked maskable interrupt request
p.319
Addition of description to
9.5.5 (2) (a) Release according to a non-maskable interrupt request or an
unmasked maskable interrupt request
p.320
Change of Figure in
9.6.1 (1) Securing the time using an on-chip time base counter
p.321
Change of Figure in
9.6.1 (2) Securing the time according to the signal level width (RESET pin input)
p.327
Addition of Caution to
10.1.4 (2) (a) Setting these registers as capture registers (CMSn0 and CMSn1 of
TMCCn1 = 0)
pp.331, 332
Addition of description to and change of bit name to bit 5 in
10.1.5 (2) Timer mode control registers C01
to C31 (TMCC01 to TMCC31)
p.347
Addition of Note to and deletion of Caution from
Figure 10-12 Cycle Measurement Operation Timing
Example
p.352
Change of description in
Figure 10-13 Example of Timing During TMDn Operation
p.354
Addition of Caution to
10.2.5 (1) Timer mode control registers D0 to D3 (TMCD0 to TMCD3)
p.362
Addition of description to Caution in
11.2.3 (1) Asynchronous serial interface mode registers 0 to 2
(ASIM0 to ASIM2)
p.365
Change of description to PEn bit = 0, FEn bit = 0, OVEn bit = 0 in
11.2.3 (2) Asynchronous serial
interface status registers 0 to 2 (ASIS0 to ASIS2)
p.366
Change of description to TXBFn bit, TXSFn bit in
11.2.3 (3) Asynchronous serial interface transmission
status registers 0 to 2 (ASIF0 to ASIF2)
p.373
Change of description in and addition of Figure to
11.2.5 (3) Continuous transmission operation
p.375
Change of description and addition of Note in
Figure 11-5 Continuous Transmission Starting Procedure
p.376
Change of description in
Figure 11-6 Continuous Transmission Ending Procedure
p.378
Modification of Figure 11-7 and addition of Caution to
Figure 11-7 Asynchronous Serial Interface
Reception Completion Interrupt Timing
p.383
Addition of Caution to
11.2.6 (2) (a) Clock select registers 0 to 2 (CKSR0 to CKSR2)
p.389
Addition of
(2)
to
11.2.7 Cautions
p.392
Addition of description to
11.3.3 (1) Clocked serial interface mode registers 0 to 2 (CSIM0 to CSIM2)
p.405
Addition of description to
12.2 (5) Successive approximation register (SAR)
p.411
Change of bit names to
12.3 (4) A/D conversion result registers (ADCR0 to ADCR7, ADCR0H to
ADCR7H)
p.437
Addition of
12.9 How to Read A/D Converter's Characteristic Table
p.444
Change of bit names in
13.3 (2) PWM buffer registers 0, 1 (PWMB0, PWMB1)
p.450
Change of block type to ports 3 and 4 in
14.2 (1) Function of each port
