CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
Figure 5-8. EDO DRAM Access Timing (2/5)
(b) Read timing (when TRHW and TW are inserted)
TRPW
Note 1
T1
WAIT (input)
D0 to D15 (I/O)
IOWR (output)
IORD (output)
LWR/LCAS (output)
UWR/UCAS (output)
WE (output)
OE (output)
RD (output)
CSn/RASm (output)
BCYST (output)
A0 to A25 (output)
CLKOUT (output)
T2
TW
TRHW
TB
TE
TW
Row address
Column address
Column address
Data
Data
Note 2
Notes 1.
TRPW is always inserted for 1 or more cycles.
2.
When a bus cycle accessing another CS space or a write cycle accessing the same CS space
follows this read cycle.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 0 to 7, m = 1, 3, 4, 6
