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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
5.3
DRAM Controller (EDO DRAM)
5.3.1 Features
• Generates the RAS, LCAS, and UCAS signals
• Can be connected directly to EDO DRAM.
• Supports the RAS hold mode.
• 4 types of DRAM can be assigned to 4 memory block spaces.
• Supports 2CAS type DRAM.
• Row and column address multiplex widths can be changed.
• Waits (0 to 3 waits) can be inserted at the following timings:
• Row address precharge wait
• Row address hold wait
• Data access wait
• Column address precharge wait
• Supports CBR refresh and CBR self-refresh.