CHAPTER 2 PIN FUNCTIONS
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User’s Manual U14359EJ4V0UM
(11) PCS0 to PCS7 (Port CS) ··· 3-state I/O
PCS0 to PCS7 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in the control mode, these pins operate as control signal outputs for when
memory and peripheral I/O are expanded externally.
The operation mode can be set to port or control mode in 1-bit units, specified by the port CS mode control
register (PMCCS).
(a) Port mode
PCS0 to PCS7 can be set to input or output in 1-bit units using the port CS mode register (PMCS).
(b) Control mode
PCS0 to PCS7 can be set to port/control mode in 1-bit units using the PMCCS register.
(i)
CS0 to CS7 (Chip select) ··· 3-state output
These are the chip select signals for the SRAM, external ROM, external peripheral I/O, and page
ROM area.
The CSn signal is assigned to memory block n (n = 0 to 7).
It becomes active while the bus cycle that accesses the corresponding memory block is activated.
In the idle state (TI), it becomes inactive.
(ii) RAS1, RAS3, RAS4, RAS6 (Row address strobe) ··· 3-state output
These are the row address strobe signals for the DRAM area and the strobe signal for the refresh
cycle.
The RASn signal is assigned to memory block n (n = 1, 3, 4, 6).
During on-page disable, after the DRAM access bus cycle ends, it becomes inactive.
During on-page enable, even after the DRAM access bus cycle ends, it remains in the active state.
During the reset period and during a bus hold period, it is in the high-impedance state, so connect it
to V
DD
via a resistor.
(iii) IOWR (I/O write) ··· 3-state output
This is the write strobe signal for external I/O during DMA flyby transfer. It indicates whether the bus
cycle currently being executed is a write cycle for external I/O during flyby transfer, or a write cycle
for the SRAM area.
Note that if the IOEN bit of the BCP register is set (1), this signal can be output even in the normal
SRAM, external ROM, or external I/O cycle.
(iv) IORD (I/O read) ··· 3-state output
This is the read strobe signal for external I/O during DMA flyby transfer. It indicates whether the bus
cycle currently being executed is a read cycle for external I/O during flyby transfer, or a read cycle
for the SRAM area.
Note that if the IOEN bit of the BCP register is set (1), this signal can be output even in the normal
SRAM, external ROM, or external I/O cycle.
