CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
348
User’s Manual U14359EJ4V0UM
10.1.8 Cautions (timer C)
Various cautions concerning timer C are shown below.
(1) If a conflict occurs between the reading of the CCCn0 register and a capture operation when the CCCn0
register is used in capture mode, an external trigger (INTP0n0) valid edge is detected and an external
interrupt request signal (INTM0n0) is generated, however, the timer value is not stored in the CCCn0 register.
(2) If a conflict occurs between the reading of the CCCn1 register and a capture operation when the CCCn1
register is used in capture mode, an external trigger (INTP0n1) valid edge is detected and an external
interrupt request signal (INTM0n1) is generated, however, the timer value is not stored in the CCCn1 register.
(3) The following bits and registers must not be rewritten during operation (TMCCEn = 1).
•
CSn2 to CSn0 bits of TMCCn0 register
•
TMCCn1 register
•
SESCn register
(4) The TMCCAEn bit of the TMCCn0 register is a TMCn reset signal. To use TMCn, first set (1) the TMCCAEn
bit.
(5) The analog noise elimination time + two cycles of the input clock are required to detect the valid edge of the
external interrupt request signal (INTP0n0 or INTP0n1) or the external clock input (TI0n0). Therefore, edge
detection will not be performed normally for changes that are less than the analog noise elimination time +
two cycles of the input clock. For details of analog noise elimination, refer to
7.3.8 Noise elimination
.
(6) The operation of an external interrupt request signal (INTM0n0 or INTM0n1) is automatically determined
according to the operating state of the capture/compare register. When the capture/compare register is used
for a capture operation, the external interrupt request signal is used for valid edge detection. When the
capture/compare register is used for a compare operation, the external interrupt request signal is used for an
interrupt indicating a match with the TMCn register.
(7) If the ENTn1 and ACTLVn bits are changed at the same time, a glitch (spike shaped noise) may be
generated in the TO0n pin output. Either create a circuit configuration that will not malfunction even if a glitch
is generated or make sure that the ENTn1 and ACTLVn bits are not changed at the same time.
Remark
n = 0 to 3
