CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
190
User’s Manual U14359EJ4V0UM
Figure 5-15. SDRAM Single Write Cycle (3/3)
(c) During on-page access
WR
TW
TWR
TWE
TWPRE
Data
On-page
SDCLK (output)
BCYST (output)
SDCKE (output)
H
Command
SDRAS (output)
H
SDCAS (output)
CSn (output)
WE (output)
LDQM (output)
UDQM (output)
Address
Address
Note
(output)
Column address
A0 to A9 (output)
A10 (output)
Address
Address
Bank address (output)
D0 to D15 (I/O)
Note
Addresses other than the bank address, A10, and A0 to A9.
Remarks 1.
The broken lines indicate the high-impedance state.
2.
n = 1, 3, 4, 6
3.
The timing chart shown here is the timing when the previous cycle accessed another CS space
or when the bus is an idle state. If access to the same CS space continues, a TW state is not
inserted (the BCYST signal becomes active in the TWR1 state).
