CHAPTER 4 BUS CONTROL FUNCTION
132
User’s Manual U14359EJ4V0UM
(2) EDO DRAM (when read, three idle states inserted)
TRPW
Note 1
T1
IOWR (output)
IORD (output)
LWR/LCAS (output)
UWR/UCAS (output)
WE (output)
OE (output)
RD (output)
CSn/RASm (output)
BCYST (output)
HLDRQ (input)
HLDAK (output)
A0 to A25 (output)
CLKOUT (input)
TE
TH
T2
TH
TI
Note 4
TI
Note 3
WAIT (input)
D0 to D15 (I/O)
Row
address
Column
address
Undefined
Note 2
Data
Notes 1.
TRPW is always inserted for 1 or more cycles.
2.
This timing applies when in the RAS hold mode.
3.
This idle state (TI) is inserted by means of a BCC register setting. The number of idle states (TI)
to be inserted depends on the timing of bus hold request acknowledgement.
4.
This idle state (TI) is independent of the BCC register setting.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 0 to 7, m = 1, 3, 4, 6
4.
Timing from DRAM access to bus hold state.
