NEC V850E/MA1, User Manual

Page: 383 / 567

CHAPTER 11 SERIAL INTERFACE FUNCTION
User’s Manual U14359EJ4V0UM
383
(2) Serial clock generation
A serial clock can be generated according to the settings of the CKSRn and BRGCn registers (n = 0 to 2).
The clock input to the 8-bit counter is selected according to the TPSn3 to TPSn0 bits of the CKSRn register.
The 8-bit counter divisor value can be selected according to the BRGn7 to BRGn0 bits of the BRGCn
register.
(a) Clock select registers 0 to 2 (CKSR0 to CKSR2)
The CKSRn register is an 8-bit register for selecting the input block according to the TPSn3 to TPSn0
bits. The clock selected by the TPSn3 to TPSn0 bits becomes the basic clock of the transmission/
reception module. Its frequency is referred to as f
XCLK
.
These registers can be read or written in 8-bit units.
Cautions 1. The maximum allowable frequency of the basic clock (f
XCLK
) is 25 MHz. Therefore,
when the system clock’s frequency is 50 MHz, bits TPSn3 to TPSn0 cannot be set to
0000B (n = 0 to 2).
If the system clock frequency is 50 MHz, set the TPSn3 to TPSn0 bits to a value
other than 0000B and set the UARTCAEn bit of the ASIMn register to 1.
2. If the TPSn3 to TPSn0 bits are to be overwritten, the UARTCAEn bit of the ASIMn
register should be set to 0 first.
7 6 5 4 3 2 1 0 Address After reset
CKSR0 0 0 0 0 TPS03 TPS02 TPS01 TPS00 FFFFFA06H 00H
CKSR1 0 0 0 0 TPS13 TPS12 TPS11 TPS10 FFFFFA16H 00H
CKSR2 0 0 0 0 TPS23 TPS22 TPS21 TPS20 FFFFFA26H 00H
Bit position Bit name Function
Specifies the basic clock.
TPSn3 TPSn2 TPSn1 TPSn0 Basic clock (f
XCLK
)
0 0 0 0 f
XX
0 0 0 1 f
XX
/2
0 0 1 0 f
XX
/4
0 0 1 1 f
XX
/8
0 1 0 0 f
XX
/16
0 1 0 1 f
XX
/32
0 1 1 0 f
XX
/64
0 1 1 1 f
XX
/128
1 0 0 0 f
XX
/256
1 0 0 1 f
XX
/512
1 0 1 0 f
XX
/1,024
1 0 1 1 f
XX
/2,048
1 1 Arbitrary Arbitrary Setting prohibited
3 to 0 TPSn3 to
TPSn0
(n = 0 to 2)
Remark f
XX
: Internal system clock