CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
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Bit position
Bit name
Function
Row Address Hold Wait Control
Specifies the number of wait states inserted as row address hold time.
RHC1n
RHC0n
Number of wait states inserted
0
0
0
0
1
1
1
0
2
1
1
3
11, 10
RHC1n,
RHC0n
(n = 1, 3,
4, 6)
Data Access Programmable Wait Control
Specifies the number of wait states inserted as data access time during DRAM access.
DAC1n
DAC0n
Number of wait states inserted
0
0
0
0
1
1
1
0
2
1
1
3
9, 8
DAC1n,
DAC0n
(n = 1, 3,
4, 6)
Column Address Pre-charge Control
Specifies the number of wait states inserted as column address precharge time.
CPC1n
CPC0n
Number of wait states inserted
0
0
0 (at least 1 wait is always inserted during on-page write access)
0
1
1
1
0
2
1
1
3
7, 6
CPC1n,
CPC0n
(n = 1, 3,
4, 6)
4
RHDn
(n = 1, 3,
4, 6)
RAS Hold Disable
Sets the RAS hold mode.
If access to DRAM during on-page operation is not continuous and another space is
accessed midway, the RASn signal is maintained in the active state (low level) during the
time the other space is being accessed in the RAS hold mode. In this way, if access
continues in the same DRAM row address following access of the other space, on-page
operation can be continued.
0: RAS hold mode enabled
1: RAS hold mode disabled
