User’s Manual U14359EJ4V0UM
14
5.3.4
DRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6) ......................................162
5.3.5
DRAM access ............................................................................................................................165
5.3.6
Refresh control function .............................................................................................................170
5.3.7
Self-refresh control function .......................................................................................................175
5.4
DRAM Controller (SDRAM) .................................................................................................... 177
5.4.1 Features .....................................................................................................................................177
5.4.2 SDRAM
connection ....................................................................................................................177
5.4.3
Address multiplex function .........................................................................................................178
5.4.4
SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6)....................................180
5.4.5 SDRAM
access ..........................................................................................................................182
5.4.6
Refresh control function .............................................................................................................196
5.4.7
Self-refresh control function .......................................................................................................201
5.4.8
SDRAM initialization sequence ..................................................................................................203
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)..................................................................... 206
6.1
Features ................................................................................................................................... 206
6.2
Configuration .......................................................................................................................... 207
6.3
Control Registers.................................................................................................................... 208
6.3.1
DMA source address registers 0 to 3 (DSA0 to DSA3) ..............................................................208
6.3.2
DMA destination address registers 0 to 3 (DDA0 to DDA3) .......................................................210
6.3.3
DMA byte count registers 0 to 3 (DBC0 to DBC3)......................................................................212
6.3.4
DMA addressing control registers 0 to 3 (DADC0 to DADC3)....................................................213
6.3.5
DMA channel control registers 0 to 3 (DCHC0 to DCHC3) ........................................................215
6.3.6
DMA disable status register (DDIS) ...........................................................................................216
6.3.7
DMA restart register (DRST) ......................................................................................................216
6.3.8
DMA terminal count output control register (DTOC)...................................................................217
6.3.9
DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) ..............................................................218
6.4
DMA Bus States ...................................................................................................................... 221
6.4.1
Types of bus states ....................................................................................................................221
6.4.2
DMAC bus cycle state transition ................................................................................................223
6.5
Transfer Modes ....................................................................................................................... 224
6.5.1
Single transfer mode ..................................................................................................................224
6.5.2
Single-step transfer mode ..........................................................................................................226
6.5.3
Block transfer mode ...................................................................................................................227
6.6
Transfer Types ........................................................................................................................ 228
6.6.1
2-cycle transfer...........................................................................................................................228
6.6.2
Flyby transfer .............................................................................................................................244
6.7
Transfer Object ....................................................................................................................... 255
6.7.1
Transfer type and transfer object ...............................................................................................255
6.7.2
External bus cycles during DMA transfer ...................................................................................256
6.8
DMA Channel Priorities.......................................................................................................... 256
6.9
Next Address Setting Function ............................................................................................. 257
6.10 DMA Transfer Start Factors ................................................................................................... 258
6.11 Terminal Count Output upon DMA Transfer End ................................................................ 259
6.12 Forcible Interruption............................................................................................................... 259
