CHAPTER 11 SERIAL INTERFACE FUNCTION
User’s Manual U14359EJ4V0UM
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(4) Receive operation
The awaiting reception state is set by setting UARTCAEn to 1 in the ASIMn register and then setting RXEn to
1 in the ASIMn register. RXDn pin sampling begins and a start bit is detected. When the start bit is detected,
the receive operation begins, and data is stored sequentially in the receive shift register according to the baud
rate that was set. A reception completion interrupt (INTSRn) is generated each time the reception of one
frame of data is completed. Normally, the receive data is transferred from the receive buffer (RXBn) to
memory by this interrupt servicing (n = 0 to 2).
(a) Reception enabled state
The receive operation is set to the reception enabled state by setting the RXEn bit in the ASIMn register
to 1 (n = 0 to 2).
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RXEn = 1: Reception enabled state
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RXEn = 0: Reception disabled state
However, when the reception enabled state is set, to use UART0 and UART1, which share pins with
clocked serial interfaces 0 and 1 (CSI0 and CSI1), the operation of CSIn must be disabled by setting the
CSICAEn bit of clocked serial interface mode registers 0 and 1 (CSIM0 and CSIM1) to 0 (n = 0 to 2).
In the reception disabled state, the reception hardware stands by in the initial state. At this time, the
contents of the receive buffer are retained, and no reception completion interrupt or reception error
interrupt is generated.
(b) Starting a receive operation
A receive operation is started by the detection of a start bit.
The RXDn pin is sampled using the serial clock from the baud rate generator (BRGn) (n = 0 to 2).
(c) Reception completion interrupt
When RXEn = 1 in the ASIMn register and the reception of one frame of data is completed (the stop bit is
detected), a reception completion interrupt (INTSRn) is generated and the receive data within the receive
shift register is transferred to RXBn at the same time (n = 0 to 2).
Also, if an overrun error occurs, the receive data at that time is not transferred to the receive buffer
(RXBn), and either a reception completion interrupt (INTSRn) or a reception error interrupt (INTSERn) is
generated according to the setting of ISRMn bit of the ASIMn register.
If a parity error or framing error occurs during reception operation, the reception operation continues up
to the position at which the stop bit is received. After completion of reception, a reception completion
interrupt (INTSRn) or reception error interrupt (INTSERn) occurs, according to the setting of the ISRMn
bit of the ASIMn register (the receive data in the receive shift register is transferred to RXBn).
If the RXEn bit is reset (0) during a receive operation, the receive operation is immediately stopped. The
contents of the receive buffer (RXBn) and of the asynchronous serial interface status register (ASISn) at
this time do not change, and no reception completion interrupt (INTSRn) or reception error interrupt
(INTSERn) is generated.
No reception completion interrupt is generated when RXEn = 0 (reception is disabled).
