CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
Figure 5-8. EDO DRAM Access Timing (4/5)
(d) Write timing (when no waits are inserted)
TRPW
Note 1
T1
Row address
Data
WAIT (input)
D0 to D15 (I/O)
(During Read to Write)
IOWR (output)
IORD (output)
LWR/LCAS (output)
UWR/UCAS (output)
WE (output)
OE (output)
RD (output)
CSn/RASm (output)
BCYST (output)
A0 to A25 (output)
CLKOUT (output)
TCPW
Note 1
TB
T2
TCPW
Note 1
TE
TB
Column address
Column address
Column address
Data
Data
Data
Data
D0 to D15 (I/O)
(During Read to Write)
Data
Data
Data
Note 2
Notes 1.
TRPW and TCPW are always inserted for 1 or more cycles.
2.
When a bus cycle accessing another CS space or a read cycle accessing the same CS space
follows this write cycle.
Remarks 1.
The broken lines indicate the high-impedance state.
2.
n = 0 to 7, m = 1, 3, 4, 6
