NEC V850E/MA1, User Manual

Page: 329 / 567

CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
User’s Manual U14359EJ4V0UM
329
10.1.5 Timer C control registers
(1) Timer mode control registers C00 to C30 (TMCC00 to TMCC30)
The TMCCn0 registers control the operation of TMCn (n = 0 to 3). These registers can be read or written in
8-bit or 1-bit units.
Be sure to set bits 3 and 2 to 0. If they are set to 1, the operation is not guaranteed.
Cautions 1. The TMCCAEn and other bits cannot be set at the same time. The other bits and the
registers of the other TMCn unit should always be set after the TMCCAEn bit has been
set. Also, to use external pins related to the timer function when timer C is used, be
sure to set (1) the TMCCAEn bit after setting the external pins to control mode.
2. When conflict occurs between an overflow and a TMCCn0 register write, the OVFn bit
value becomes the value written during the TMCCn0 register write (n = 0 to 3).
(1/2)
<7> 6 5 4 3 2 <1> <0> Address After reset
TMCC00 OVF0 CS02 CS01 CS00 0 0 TMCCE0
TMCCAE0
FFFFF606H 00H
TMCC10 OVF1 CS12 CS11 CS10 0 0 TMCCE1
TMCCAE1
FFFFF616H 00H
TMCC20 OVF2 CS22 CS21 CS20 0 0 TMCCE2
TMCCAE2
FFFFF626H 00H
TMCC30 OVF3 CS32 CS31 CS30 0 0 TMCCE3
TMCCAE3
FFFFF636H 00H
Bit position Bit name Function
7 OVFn
(n = 0 to 3)
Overflow
This is a flag that indicates TMCn overflow (n = 0 to 3).
0: No overflow occurs
1: Overflow occurs
When TMCn has counted up from FFFFH to 0000H, the OVFn bit becomes 1 and
an overflow interrupt request (INTOV0n) is generated at the same time. However,
if TMCn is cleared to 0000H after a match at FFFFH when the CCCn0 register is
set to compare mode (CMSn0 bit of TMCCn1 register = 1) and clearing is enabled
for a match when TMCn and CCCn0 are compared (CCLRn bit of TMCCn1 register
= 1), then TMCn is considered to be cleared and the OVFn bit does not become 1.
Also, no INTOV0n interrupt is generated.
The OVFn bit retains the value 1 until 0 is written directly or until an asynchronous
reset is performed because the TMCCAEn bit is 0. An interrupt operation due to an
overflow is independent of the OVFn bit, and the interrupt request flag (OVIFn) for
INTOV0n is not affected even if the OVFn bit is manipulated. If an overflow occurs
while the OVFn bit is being read, the flag value changes, and the change is
reflected when the next read operation occurs.