NEC V850E/MA1, User Manual

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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
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User’s Manual U14359EJ4V0UM
7.3.6 In-service priority register (ISPR)
This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request
is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and
remains set while the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority is
automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned from non-maskable
interrupt servicing or exception processing.
This register is read-only in 8-bit or 1-bit units.
Address
FFFFF1FAH
<7>
ISPR7 ISPR
<6>
ISPR6
<5>
ISPR5
<4>
ISPR4
<3>
ISPR3
<2>
ISPR2
<1>
ISPR1
<0>
ISPR0
After reset
00H
Bit position Bit name Function
7 to 0 ISPR7 to ISPR0
In-Service Priority Flag
Indicates priority of interrupt currently acknowledged
0: Interrupt request with priority n not acknowledged
1: Interrupt request with priority n acknowledged
Remark n = 0 to 7 (priority level)
7.3.7 Maskable interrupt status flag (ID)
The ID flag is bit 5 of the PSW and controls the maskable interrupt’s operating state, and stores control
information regarding enabling or disabling of interrupt requests.
31 0
PSW
After reset
00000020H
7
NP
6
EP
5
ID
4
SAT
3
CY
2
OV
1
S Z
8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit position Bit name Function
5 ID
Interrupt Disable
Indicates whether maskable interrupt servicing is enabled or disabled.
0: Maskable interrupt request acknowledgement enabled
1: Maskable interrupt request acknowledgement disabled (pending)
This bit is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its
value is also modified by the RETI instruction or LDSR instruction when
referencing the PSW.
Non-maskable interrupt requests and exceptions are acknowledged regardless
of this flag. When a maskable interrupt is acknowledged, the ID flag is
automatically set to 1 by hardware.
The interrupt request generated during the acknowledgement disabled period
(ID = 1) is acknowledged when the xxIFn bit of xxICn is set to 1, and the ID flag
is reset to 0.