CHAPTER 9 CLOCK GENERATION FUNCTION
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User’s Manual U14359EJ4V0UM
9.5
Power-Save Control
9.5.1 Overview
The power-save function has the following three modes.
(1) HALT mode
In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU’s
operation clock stops. Since the supply of clocks to on-chip peripheral functions other than the CPU
continues, operation continues. The power consumption of the overall system can be reduced by intermittent
operation using a combination of the HALT mode and the normal operation mode.
The system is switched to HALT mode by a specific instruction (the HALT instruction).
(2) IDLE mode
In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of
internal system clocks is stopped, which causes the overall system to stop.
When the system is released from IDLE mode, it can be switched to normal operation mode quickly because
the oscillator’s oscillation stabilization time does not need to be secured.
The system is switched to IDLE mode by a PSMR register setting.
IDLE mode is located midway between software STOP mode and HALT mode in relation to the clock
stabilization time and current consumption. It is used for situations in which a low-current-consumption mode
is to be used and the clock stabilization time is to be eliminated after the mode is released.
(3) Software STOP mode
In this mode, the overall system is stopped by stopping the clock generator (oscillator and PLL synthesizer).
The system enters an ultra-low-power-consumption state in which only leakage current is lost.
The system is switched to software STOP mode by a PSMR register setting.
(a) PLL mode
The system is switched to software STOP mode by setting the register using software. The PLL
synthesizer’s clock output is stopped at the same time the oscillator is stopped. After software STOP
mode is released, the oscillator’s oscillation stabilization time must be secured until the system clock
stabilizes. Also, PLL lockup time may be required depending on the program. When a resonator or
external clock is connected, following the release of the software STOP mode, execution of the program
is started after the count time of the time base counter has elapsed.
(b) Direct mode
To stop the clock, set the X1 pin to low level. After the release of software STOP mode, execution of the
program is started after the count time of the time base counter has elapsed.
