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User’s Manual U14359EJ4V0UM

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6.13 Forcible Termination .............................................................................................................. 260

6.14 Times Related to DMA Transfer ............................................................................................ 261

6.15 Maximum Response Time for DMA Transfer Request ....................................................... 261

6.16 One-Time Transfer During Single Transfer via DMARQ0 to DMARQ3 Signals................ 262

6.17 Cautions .................................................................................................................................. 263

6.17.1

Interrupt factors.......................................................................................................................... 263

6.18 DMA Transfer End .................................................................................................................. 263

CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION ............................................... 264

7.1

Features................................................................................................................................... 264

7.2

Non-Maskable Interrupts ....................................................................................................... 267

7.2.1

Operation ................................................................................................................................... 268

7.2.2

Restore ...................................................................................................................................... 270

7.2.3

Non-maskable interrupt status flag (NP) .................................................................................... 271

7.2.4

Noise elimination........................................................................................................................ 271

7.2.5

Edge detection function ............................................................................................................. 271

7.3

Maskable Interrupts................................................................................................................ 272

7.3.1

Operation ................................................................................................................................... 272

7.3.2

Restore ...................................................................................................................................... 274

7.3.3

Priorities of maskable interrupts................................................................................................. 275

7.3.4

Interrupt control register (xxICn) ................................................................................................ 279

7.3.5

Interrupt mask registers 0 to 3 (IMR0 to IMR3) .......................................................................... 282

7.3.6

In-service priority register (ISPR) ............................................................................................... 283

7.3.7

Maskable interrupt status flag (ID) ............................................................................................. 283

7.3.8

Noise elimination........................................................................................................................ 284

7.3.9

Interrupt trigger mode selection ................................................................................................. 284

7.4

Software Exception ................................................................................................................ 288

7.4.1

Operation ................................................................................................................................... 288

7.4.2

Restore ...................................................................................................................................... 289

7.4.3

Exception status flag (EP).......................................................................................................... 290

7.5

Exception Trap........................................................................................................................ 291

7.5.1

Illegal opcode definition ............................................................................................................. 291

7.5.2

Debug trap ................................................................................................................................. 293

7.6

Multiple Interrupt Servicing Control ..................................................................................... 295

7.7

Interrupt Latency Time........................................................................................................... 297

7.8

Periods in Which Interrupts Are Not Acknowledged.......................................................... 298

CHAPTER 8 PRESCALER UNIT (PRS) ............................................................................................ 299

CHAPTER 9 CLOCK GENERATION FUNCTION............................................................................. 300

9.1

Features................................................................................................................................... 300

9.2

Configuration .......................................................................................................................... 300

9.3

Input Clock Selection ............................................................................................................. 301

9.3.1

Direct mode ............................................................................................................................... 301

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Summary of Contents for V850E/MA1

Page 1: ...Microcontroller Hardware User s Manual PD703103A PD703105A PD703106A PD703106A A PD703107A PD703107A A PD70F3107A PD70F3107A A Printed in Japan Document No U14359EJ4V0UM00 4th edition Date Published M...

Page 2: ...2 User s Manual U14359EJ4V0UM MEMO...

Page 3: ...o the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CM...

Page 4: ...hird parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknow...

Page 5: ...0 800 729 9288 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore...

Page 6: ...ge of description in 4 5 1 Number of access clocks p 104 Addition of description to 4 5 2 1 Bus size configuration register BSC p 105 Addition of Caution to 4 5 3 1 Endian configuration register BEC p...

Page 7: ...of description in Figure 10 13 Example of Timing During TMDn Operation p 354 Addition of Caution to 10 2 5 1 Timer mode control registers D0 to D3 TMCD0 to TMCD3 p 362 Addition of description to Caut...

Page 8: ...register PMC2 p 475 Change of block type to P30 and P33 in 14 3 4 1 Operation in control mode p 478 Change of block type to P40 and P43 in 14 3 5 1 Operation in control mode p 483 Addition of Caution...

Page 9: ...ripheral functions Instruction format and instruction set Flash memory programming Interrupts and exceptions Pipeline operation How to Read This Manual It is assumed that the readers of this manual ha...

Page 10: ...on Information requiring particular attention Remark Supplementary information Numeric representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Prefix indicating power of 2 address space mem...

Page 11: ...iler package Assembly Language U15027E ID850 Ver 2 40 Integrated debugger Operation WindowsTM Based U15181E SM850 Ver 2 40 System simulator Operation Windows Based U15182E SM850 Ver 2 00 or later Syst...

Page 12: ...Connection of Unused Pins 62 2 5 Pin I O Circuits 64 CHAPTER 3 CPU FUNCTION 65 3 1 Features 65 3 2 CPU Register Set 66 3 2 1 Program register set 67 3 2 2 System register set 68 3 3 Operating Modes 70...

Page 13: ...les in which wait function is valid 125 4 7 Idle State Insertion Function 126 4 8 Bus Hold Function 127 4 8 1 Function outline 127 4 8 2 Bus hold procedure 128 4 8 3 Operation in power save mode 128 4...

Page 14: ...ount registers 0 to 3 DBC0 to DBC3 212 6 3 4 DMA addressing control registers 0 to 3 DADC0 to DADC3 213 6 3 5 DMA channel control registers 0 to 3 DCHC0 to DCHC3 215 6 3 6 DMA disable status register...

Page 15: ...n 272 7 3 2 Restore 274 7 3 3 Priorities of maskable interrupts 275 7 3 4 Interrupt control register xxICn 279 7 3 5 Interrupt mask registers 0 to 3 IMR0 to IMR3 282 7 3 6 In service priority register...

Page 16: ...onfiguration of timer C 324 10 1 4 Timer C 325 10 1 5 Timer C control registers 329 10 1 6 Timer C operation 334 10 1 7 Application examples timer C 341 10 1 8 Cautions timer C 348 10 2 Timer D 349 10...

Page 17: ...rigger Mode 422 12 6 1 Select mode operation 423 12 6 2 Scan mode operation 427 12 7 Operation in External Trigger Mode 431 12 7 1 Select mode operations external trigger select 431 12 7 2 Scan mode o...

Page 18: ...Programmer 509 16 3 Programming Environment 514 16 4 Communication Mode 514 16 5 Pin Connection 515 16 5 1 MODE2 VPP pin 515 16 5 2 Serial interface pin 515 16 5 3 RESET pin 517 16 5 4 NMI pin 517 16...

Page 19: ...amming mode control register FLPMC 531 16 7 13 Calling device internal processing 533 16 7 14 Erasing flash memory flow 536 16 7 15 Successive writing flow 537 16 7 16 Internal verify flow 538 16 7 17...

Page 20: ...44 5 3 Examples of Connection to Page ROM 151 5 4 On Page Off Page Judgment During Page ROM Connection 152 5 5 Page ROM Access Timing 155 5 6 Examples of Connection to DRAM 160 5 7 Row Address Column...

Page 21: ...ess Timing During DMA Flyby Transfer 250 6 19 DRAM Access Timing During DMA Flyby Transfer 251 6 20 Buffer Register Configuration 257 6 21 Terminal Count Signal TCn Timing Example 259 6 22 Example of...

Page 22: ...ronous Serial Interface Block Diagram 361 11 2 Asynchronous Serial Interface Transmit Receive Data Format 370 11 3 Asynchronous Serial Interface Transmission Completion Interrupt Timing 372 11 4 Conti...

Page 23: ...er Scan 1 Trigger 428 12 14 Example of 4 Trigger Mode Operation Timer Trigger Scan 4 Triggers 430 12 15 Example of 1 Buffer Mode Operation External Trigger Select 1 Buffer 431 12 16 Example of 4 Buffe...

Page 24: ...161F1 EN4 for V850E MA1 Flash Memory Programming 512 16 3 Outline of Self Programming 521 16 4 Outline of Self Programming Interface 523 16 5 Example of Self Programming Circuit Configuration 523 16...

Page 25: ...Using Power Save Control 308 9 2 Operation Status in HALT Mode 312 9 3 Operation After HALT Mode Is Released by Interrupt Request 313 9 4 Operation Status in IDLE Mode 315 9 5 Operation After IDLE Mo...

Page 26: ...Wiring of Adapter for V850E MA1 Flash Memory Programming FA 161F1 EN4 513 16 3 List of Communication Modes 519 16 4 Function List 522 16 5 Software Environmental Conditions 525 16 6 Self Programming...

Page 27: ...y interfaces including separately configured address 26 bits and data 16 bits buses and SDRAM and ROM interfaces as well as on chip memory controllers that can be directly linked to EDO DRAM page ROM...

Page 28: ...data use Chip select output function 8 spaces Memory block division function 2 4 8 MB block Programmable wait function Idle state insertion function External bus interface 16 bit data bus address data...

Page 29: ...unit 16 bit timer event counter 4 channels 16 bit timers 4 16 bit capture compare registers 8 16 bit interval timer 4 channels Serial interfaces SIO Asynchronous serial interface UART Clocked serial...

Page 30: ...EN4 161 pin plastic FBGA 13 13 Standard for general purpose electronic systems PD703107AF1 EN4 161 pin plastic FBGA 13 13 Standard for general purpose electronic systems PD70F3107AF1 EN4 161 pin plas...

Page 31: ...ANI7 V DD V SS TC3 INTP113 P27 TC2 INTP112 P26 TC1 INTP111 P25 TC0 INTP110 P24 TO02 P23 INTP021 P22 TI020 INTP020 P21 NMI P20 V DD V SS ADTRG INTP123 P37 INTP122 P36 INTP121 P35 RXD2 INTP120 P34 TXD2...

Page 32: ...9 A18 PAH2 D1 VSS A4 A5 PAL5 B10 A21 PAH5 D2 D10 PDL10 A5 B11 A25 PAH9 D3 D14 PDL14 A6 A9 PAL9 B12 SDCLK PCD1 D4 A3 PAL3 A7 A12 PAL12 B13 CS1 RAS1 PCS1 D5 A6 PAL6 A8 A15 PAL15 B14 D6 A10 PAL10 A9 A17...

Page 33: ...L4 DMAAK0 PBD0 N10 CVSS G3 D0 PDL0 L5 TO02 P23 N11 SCK0 P42 G4 D6 PDL6 L6 VDD N12 AVDD AVREF G11 WAIT PCM0 L7 INTP122 P36 N13 AVSS G12 WE PCT5 L8 SI2 INTP131 P31 N14 G13 BCYST PCT7 L9 RESET P1 VDD G1...

Page 34: ...HLDRQ Hold request SCK0 to SCK2 Serial clock INTP000 INTP001 Interrupt request from peripherals SDCAS SDRAM column address strobe INTP010 INTP011 SDCKE SDRAM clock enable INTP020 INTP021 SDCLK SDRAM...

Page 35: ...45 P30 to P37 P21 to P27 P20 P10 to P13 P00 to P07 CG System controller BCU CLKOUT CKSEL X1 X2 CVDD CVSS MODE0 MODE1 MODE2 VPP Note 3 RESET VDD VSS UART0 CSI0 UART1 CSI1 UART2 CSI2 ADC SO0 TXD0 SI0 RX...

Page 36: ...roller generates the SDRAS SDCAS UDQM and LDQM signals and performs access control for SDRAM CAS latency 2 and 3 are supported and the burst length is fixed to 1 A refresh function that supports the C...

Page 37: ...e input clock fX using an on chip PLL or 1 2 the input clock when an on chip PLL is not used as the internal system clock fXX As the input clock an external oscillator is connected to pins X1 and X2 o...

Page 38: ...t I O External bus interface control signal output Port CT 6 bit I O External bus interface control signal output Port CM 6 bit I O Wait insertion signal input internal system clock output external bu...

Page 39: ...ts DMARQ3 INTP103 P10 PWM1 P11 INTP010 TI010 P12 INTP011 P13 I O Port 1 4 bit I O port Input output can be specified in 1 bit units TO01 P20 Input NMI P21 INTP020 TI020 P22 INTP021 P23 TO02 P24 TC0 IN...

Page 40: ...nput output can be specified in 1 bit units DMAAK0 to DMAAK3 PCM0 WAIT PCM1 CLKOUT BUSCLK PCM2 HLDAK PCM3 HLDRQ PCM4 REFRQ PCM5 I O Port CM 6 bit I O port Input output can be specified in 1 bit units...

Page 41: ...n PAH0 to PAH9 I O Port AH 8 10 bit I O port Input output can be specified in 1 bit units A16 to A25 PAL0 to PAL15 I O Port AL 8 16 bit I O port Input output can be specified in 1 bit units A0 to A15...

Page 42: ...ut or timer C1 external capture trigger input P12 INTP020 P21 TI020 INTP021 External maskable interrupt request input or timer C2 external capture trigger input P22 INTP030 P50 TI030 INTP031 Input Ext...

Page 43: ...r input P37 INTP123 DMARQ0 P04 INTP100 DMARQ1 P05 INTP101 DMARQ2 P06 INTP102 DMARQ3 Input DMA request signal input P07 INTP103 DMAAK0 PBD0 DMAAK1 PBD1 DMAAK2 PBD2 DMAAK3 Output DMA acknowledge signal...

Page 44: ...CS4 PCS4 RAS4 CS5 PCS5 IORD CS6 PCS6 RAS6 CS7 Output Chip select signal output PCS7 RAS1 PCS1 CS1 RAS3 PCS3 CS3 RAS4 PCS4 CS4 RAS6 Output Row address strobe signal output for DRAM PCS6 CS6 IOWR Output...

Page 45: ...ck generator s operating mode AVREF Input Reference voltage applied to A D converter AVDD AVDD Positive power supply for A D converter AVREF AVSS Ground potential for A D converter CVDD Positive power...

Page 46: ...1 CBR Operating Hi Z LDQM UDQM PCT0 PCT1 H Operating Hi Z RD PCT4 Hi Z Hi Z H Operating Hi Z WE PCT5 Hi Z Hi Z H Operating Hi Z OE PCT6 Hi Z Hi Z H Operating Hi Z BCYST PCT7 Hi Z Hi Z H Operating Hi Z...

Page 47: ...using the PMC0 register i PWM0 Pulse width modulation output This pin outputs the PWM pulse signal ii TI000 Timer input input This is the external count clock input pin for timer C0 iii TO00 Timer ou...

Page 48: ...rt 1 mode control register PMC1 a Port mode P10 to P13 can be set to input or output in 1 bit units using the port 1 mode register PM1 b Control mode P10 to P13 can be set to port control mode in 1 bi...

Page 49: ...dge is input it operates as an NMI input b Control mode P21 to P27 can be set to port control mode in 1 bit units using the PMC2 register i NMI Non maskable interrupt request input This is the non mas...

Page 50: ...n 1 bit units using the port 3 mode register PM3 b Control mode P30 to P37 can be set to port control mode in 1 bit units using the PMC3 register i TXD2 Transmit data output This pin outputs the seria...

Page 51: ...ster PMC4 a Port mode P40 to P45 can be set to input or output in 1 bit units using the port 4 mode register PM4 b Control mode P40 to P45 can be set to port control mode in 1 bit units using the PMC4...

Page 52: ...request from peripherals input These are external interrupt request input pins and the external capture trigger input pins for timer C3 7 P70 to P77 Port 7 3 state I O P70 to P77 function as an 8 bit...

Page 53: ...DMA transfers 9 PCM0 to PCM5 Port CM 3 state I O PCM0 to PCM5 function as a 6 bit I O port that can be set to input or output in 1 bit units Besides functioning as a port in the control mode these pi...

Page 54: ...s occurs either when the V850E MA1 completes execution of the current bus cycle or immediately if no bus cycle is being executed then the HLDAK signal is set as active and the bus is released In order...

Page 55: ...hows whether the bus cycle currently being executed is a write cycle for the SRAM external ROM or external peripheral I O area For the data bus the lower byte becomes valid If the bus cycle is a lower...

Page 56: ...signal shows that the bus cycle currently being executed is a write cycle for the DRAM area In the idle state TI it becomes inactive ix OE Output enable 3 state output This signal shows that the bus...

Page 57: ...ut These are the row address strobe signals for the DRAM area and the strobe signal for the refresh cycle The RASn signal is assigned to memory block n n 1 3 4 6 During on page disable after the DRAM...

Page 58: ...D0 to PCD3 can be set to port or control mode in 1 bit units using the PMCCD register i SDCKE SDRAM clock enable 3 state output This is the SDRAM clock enable output signal It becomes inactive in self...

Page 59: ...the fall of the CLKOUT signal in the T1 state In the idle state TI the address of the bus cycle immediately before is retained 14 PAL0 to PAL15 Port AL 3 state I O PAL0 to PAL15 function as an 8 or 1...

Page 60: ...ns become high impedance 16 CKSEL Clock generator operating mode select input This is an input pin used to specify the clock generator s operating mode 17 MODE0 to MODE2 Mode input These are input pin...

Page 61: ...the A D converter 25 AVSS Analog ground This is the ground pin for the A D converter 26 AVREF Analog reference voltage input This is the reference voltage supply pin for the A D converter 27 VPP Progr...

Page 62: ...irectly P21 INTP020 TI020 P22 INTP021 5 AC P23 TO02 5 P24 TC0 INTP110 to P27 TC3 INTP113 P30 SO2 INTP130 P31 SI2 INTP131 P32 SCK2 INTP132 P33 TXD2 INTP133 P34 RXD2 INTP120 P35 INTP121 P36 INTP122 P37...

Page 63: ...endently connect to VSS via a resistor PCT0 LCAS LWR LDQM PCT1 UCAS UWR UDQM PCT4 RD PCT5 WE PCT6 OE PCT7 BCYST PCS0 CS0 PCS1 CS1 RAS1 PCS2 CS2 IOWR PCS3 CS3 RAS3 PCS4 CS4 RAS4 PCS5 CS5 IORD PCS6 CS6...

Page 64: ...e 1 Type 2 Type 5 P ch N ch IN VDD IN Schmitt triggered input with hysteresis characteristics P ch N ch VDD IN OUT Data Output disable Input enable Type 5 AC P ch N ch VDD IN OUT Data Output disable I...

Page 65: ...Minimum instruction cycle 20 ns 50 MHz internal operation Memory space Program space 64 MB linear Data space 4 GB linear Thirty two 32 bit general purpose registers Internal 32 bit architecture Five s...

Page 66: ...r26 r27 r28 r29 r30 r31 Zero register Assembler reserved register Stack pointer SP Global pointer GP Text pointer TP Element pointer EP Link pointer LP PC Program counter PSW Program status word ECR I...

Page 67: ...time OS does not use r2 it can be used as a variable register Table 3 1 Program Registers Name Usage Operation r0 Zero register Always holds 0 r1 Assembler reserved register Working register for gener...

Page 68: ...gister during CALLT execution CTPSW 18 Status saving register during exception debug trap DBPC Note 2 19 Status saving register during exception debug trap DBPSW Note 2 20 CALLT base pointer CTBP 21 t...

Page 69: ...o clear 0 this bit load data in PSW Note that in a general arithmetic operation this bit is neither set 1 nor cleared 0 0 Not saturated 1 Saturated 3 CY This flag is set if a carry or borrow occurs as...

Page 70: ...set entry address and instruction processing starts The internal ROM area is mapped from address 100000H b ROMless modes 0 1 After system reset is cleared each pin related to the bus interface enters...

Page 71: ...E2 MODE1 MODE0 Operating Mode Remarks L L L ROMless mode 0 16 bit data bus L L H ROMless mode 1 8 bit data bus L H L Single chip mode 0 Internal ROM area is allocated from address 000000H L H H Normal...

Page 72: ...to 4 GB of linear address space data space during operand addressing data access Also in instruction address addressing a maximum of 64 MB of linear address space program space is supported Figure 3 1...

Page 73: ...he image of the virtual addressing space Physical address x0000000H can be seen as CPU address 00000000H and in addition can be seen as address 10000000H address 20000000H address E0000000H or address...

Page 74: ...mit address and upper limit address become contiguous Caution The 4 KB area of 03FFF000H to 03FFFFFFH can be seen as an image of 0FFFF000H to 0FFFFFFFH This area is access prohibited Therefore do not...

Page 75: ...nternal RAM area Access prohibitedNote External memory area Internal ROM area External memory area Internal ROM area External memory area Single chip mode 0 Single chip mode 1 ROMless mode 0 1 256 MB...

Page 76: ...Access prohibitedNote External memory area Internal ROM area External memory area Internal ROM area External memory area Single chip mode 0 Single chip mode 1 ROMless mode 0 1 256 MB 1 MB 1 MB 4 KB x...

Page 77: ...hysical internal ROM flash memory In single chip mode 0 Addresses 000000H to 03FFFFH In single chip mode 1 Addresses 100000H to 13FFFFH b Interrupt exception table The V850E MA1 increases the interrup...

Page 78: ...000 INTM000 000000D0H INTP001 INTM001 000000E0H INTP010 INTM010 000000F0H INTP011 INTM011 00000100H INTP020 INTM020 00000110H INTP021 INTM021 00000120H INTP030 INTM030 00000130H INTP031 INTM031 000001...

Page 79: ...00330H INTST1 00000340H INTCSI2 00000350H INTSER2 00000360H INTSR2 00000370H INTST2 00000380H INTAD c Internal ROM area relocation function If set in single chip mode 1 the internal ROM area is locate...

Page 80: ...FH are provided as physical internal RAM In the PD703106A 703107A and 70F3107A the 10 KB area of addresses FFFC000H to FFFE7FFH are provided as physical internal RAM Caution The following areas are ac...

Page 81: ...e access is possible if halfword access is executed the higher 8 bits become undefined during the read operation and the lower 8 bits of data are written to the register during the write operation 3 A...

Page 82: ...hanges to the port n mode control register PMCn the external data bus width is 16 bits b In the case of ROMless mode 1 Because each pin of ports AL AH DL CS CT CM and CD enters control mode following...

Page 83: ...ontiguous 64 MB space starting from address 00000000H unconditionally corresponds to the memory map of the program space 2 Data space With the V850E MA1 a 256 MB physical address space is seen as 16 i...

Page 84: ...H x0020000H x001FFFFH x0000000H xFFFFC14H xFFFFC13H Data space Program space On chip peripheral I O On chip peripheral I O Internal RAM Internal RAM External memory Internal ROM External memory Extern...

Page 85: ...Port AL mode register L PMALL R W FFH FFFFF021H Port AL mode register H PMALH R W FFH FFFFF022H Port AH mode register PMAH R W FFFFH FFFFF022H Port AH mode register L PMAHL R W FFH FFFFF023H Port AH m...

Page 86: ...DMA source address register 0L DSA0L R W Undefined FFFFF082H DMA source address register 0H DSA0H R W Undefined FFFFF084H DMA destination address register 0L DDA0L R W Undefined FFFFF086H DMA destina...

Page 87: ...1H R W FFH FFFFF104H Interrupt mask register 2 IMR2 R W FFFFH FFFFF104H Interrupt mask register 2L IMR2L R W FFH FFFFF105H Interrupt mask register 2H IMR2H R W FFH FFFFF106H Interrupt mask register 3...

Page 88: ...R W 47H FFFFF14EH Interrupt control register CMICD3 R W 47H FFFFF150H Interrupt control register DMAIC0 R W 47H FFFFF152H Interrupt control register DMAIC1 R W 47H FFFFF154H Interrupt control registe...

Page 89: ...r 2H 8 bits ADCR2H R 00H FFFFF223H A D conversion result register 3H 8 bits ADCR3H R 00H FFFFF224H A D conversion result register 4H 8 bits ADCR4H R 00H FFFFF225H A D conversion result register 5H 8 b...

Page 90: ...configuration register 1 R W 3FC1H FFFFF4A4H SDRAM configuration register 1 SCR1 R W 0000H Refresh control register 1 R W 0000H FFFFF4A6H SDRAM refresh control register 1 RFS1 R W 0000H DRAM configur...

Page 91: ...619H Valid edge select register C1 SESC1 R W 00H FFFFF620H Timer C2 TMC2 R 0000H FFFFF622H Capture compare register C20 CCC20 R W 0000H FFFFF624H Capture compare register C21 CCC21 R W 0000H FFFFF626H...

Page 92: ...913H Receive only serial I O shift register 1 SIOE1 R 00H FFFFF914H Clocked serial interface transmit buffer register 1 SOTB1 R W 00H FFFFF920H Clocked serial interface mode register 2 CSIM2 R W 00H F...

Page 93: ...ynchronous serial interface status register 2 ASIS2 R 00H FFFFFA24H Transmit buffer register 2 TXB2 R W FFH FFFFFA25H Asynchronous serial interface transmit status register 2 ASIF2 R 00H FFFFFA26H Clo...

Page 94: ...elow to the VSWC in accordance with the operation frequency used This register can be read written in 8 bit units address FFFFF06EH initial value 77H Operation Frequency fXX Set Value of VSWC Number o...

Page 95: ...ister for Port Control Mode Switching Data bus D0 to D15 PDL0 to PDL15 Port DL PMCDL Address bus A0 to A15 PAL0 to PAL15 Port AL PMCAL Address bus A16 to A25 PAH0 to PAH9 Port AH PMCAH Chip select CS0...

Page 96: ...ndefined and the data bus control signals are not output and enter the high impedance state The external bus control signals become inactive While accessing peripheral I O the address bus outputs the...

Page 97: ...8000000H 7FFFFFFH 4000000H 3FFFFFFH 0800000H 07FFFFFH 0600000H 05FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 1 2 MB Block 0 2 MB Block 2 2 MB Block 3 2 MB 64 MB 64 MB Block 5 2 MB Block...

Page 98: ...ed below 1 Chip area select control registers 0 1 CSC0 CSC1 These registers can be read written in 16 bit units and become valid by setting each bit to 1 If different chip select signal outputs are se...

Page 99: ...block 1 access CS22 CS2 output during block 2 access CS23 CS2 output during block 3 access CS30 to CS33 Setting has no meaning CS40 to CS43 Setting has no meaning CS50 CS5 output during block 7 acces...

Page 100: ...V0UM Figure 4 1 Example When CSC0 Register Is Set to 0703H 3FFFFFFH 0600000H 05FFFFFH 0800000H 07FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 2 2 MB Block 3 2 MB Block 1 2 MB Block 0 2 MB...

Page 101: ...Type Control Function In the V850E MA1 the following external devices can be connected directly to each memory block SRAM external ROM external I O Page ROM EDO DRAM SDRAM Connected external devices a...

Page 102: ...reset 8888H 14 0 13 BT31 12 BT30 11 ME2 10 0 9 0 8 BT20 7 ME1 6 0 5 BT11 4 BT10 3 ME0 2 0 1 0 0 BT00 CS3 CS2 CS1 CS0 15 ME7 BCT1 CSn signal Address FFFFF482H After reset 8888H 14 0 13 0 12 BT70 11 ME6...

Page 103: ...of basic clocks necessary for accessing each resource is as follows Bus Cycle Configuration Resource Bus Width Instruction Fetch Operand Data Access Internal ROM 32 bits 1Note 1 5 Internal RAM 32 bit...

Page 104: ...tine until the initial setting of the BSC register is complete However it is possible to access external memory areas whose initialization settings are complete 2 When the data bus width is specified...

Page 105: ...nvalid On chip peripheral I O area Internal ROM area Internal RAM area Fetch area for external memory 1 Endian configuration register BEC This register can be read written in 16 bit units Be sure to s...

Page 106: ...annot be used Access with cast changing access size cannot be used Variables with initial values cannot be used ii It is necessary to specify the following optimization inhibit options because optimiz...

Page 107: ...i 1 1 bit test using bit and if i 1 Related optimization depending on model part Accessing the same variable in a different size Cast Mask Shift Example int i ip char c c char ip c 0xff i i i 24 24 b...

Page 108: ...ss to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data 15 8 External data bus 2n Address 7 0 7 0 Byte data 15 8 External data bus 2n 1 Address b When the data bus width is 8 bits little...

Page 109: ...st access 2nd access 7 0 7 0 Halfword data 15 8 External data bus 2n Address 15 8 2n 1 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus...

Page 110: ...8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 2 Address d When the data bus width is 8 bits big endian 1 Access to even address 2n 2 Access to odd address...

Page 111: ...External data bus 4n Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 2 Access to address 4n 1 1st access 2nd access 3rd access 7 0 7 0 Word da...

Page 112: ...ta bus 4n 2 Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 4 Access to address 4n 3 1st access 2nd access 3rd access 7 0 7 0 Word data 15 8 E...

Page 113: ...Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 2 Access to address 4n 1 1st access 2nd acc...

Page 114: ...3 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 4 Access to address 4n 3 1st access 2nd a...

Page 115: ...ata bus 4n 3 Address 15 8 4n 2 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 1 Address 15 8 4n 23 16 31 24 2 Access to address 4n 1 1st access 2nd access 3rd access 7 0 7 0 Word data 15 8 Ex...

Page 116: ...ata bus 4n 5 Address 15 8 4n 4 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 3 Address 15 8 4n 2 23 16 31 24 4 Access to address 4n 3 1st access 2nd access 3rd access 7 0 7 0 Word data 15 8...

Page 117: ...Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 1 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n Address 15 8 23 16 31 24 2 Access to address 4n 1 1st access 2nd acces...

Page 118: ...Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 4 Access to address 4n 3 1st access 2nd acc...

Page 119: ...nternal RAM area are not subject to programmable waits and ordinarily no wait access is carried out The on chip peripheral I O area is also not subject to programmable wait states with wait control pe...

Page 120: ...DW60 0 DW52 DW51 DW50 0 DW42 DW41 DW40 CS3 CS2 CS1 CS0 CS7 CS6 CS5 CS4 15 DWC1 CSn signal Address FFFFF486H After reset 7777H 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position Bit name Function Data Wai...

Page 121: ...ons 1 During an address setup wait the WAIT pin based external wait function is disabled 2 Write to the ASC register after reset and then do not change the set value 15 AC71 ASC CSn signal Address FFF...

Page 122: ...ROM and EDO DRAM cycles on the other hand the IOEN bit setting has no meaning 2 Write to the BCP register after reset and then do not change the set values 3 If the CLKOUT output mode is selected for...

Page 123: ...output LWR LCAS output IORD output Note UWR UCAS output WE output OE output RD output BCYST output A0 to A25 output Internal system clock T2 T1 CSn RASm output LBE output UBE output BUSCLK output Add...

Page 124: ...time in the sampling timing is not satisfied the wait state may or may not be inserted in the next state 4 6 3 Relationship between programmable wait and external wait A wait cycle is inserted as the...

Page 125: ...SCRm RPC1m RPC0m 1 to 3 invalid Row address hold SCRm RHC1m RHC0m 0 to 3 invalid Off page Data access wait SCRm DAC1m DAC0m 0 to 3 invalid CAS precharge SCRm CPC1m CPC0m 1 to 3 invalid Write access O...

Page 126: ...ed for all memory blocks For the timing when an idle state is inserted see the memory access timings in Chapter 5 1 Bus cycle control register BCC This register can be read written in 16 bit units Cau...

Page 127: ...esses Between first and second accesses Word access for odd address Between second and third accesses 16 bits Halfword access for odd address Between first and second accesses Between first and second...

Page 128: ...Normal state Bus hold state Normal state HLDAK output HLDRQ input 1 2 3 4 5 6 7 8 9 4 8 3 Operation in power save mode In the software STOP or IDLE mode the internal system clock is stopped Consequen...

Page 129: ...t RD output CSn RASm output BCYST output HLDRQ input HLDAK output A0 to A25 output CLKOUT input TH TH TI Note 1 TI Note 1 LBE output WAIT input D0 to D15 I O Data UBE output Address Notes 1 This idle...

Page 130: ...utput A0 to A25 output CLKOUT input TH TH TI Note 1 TI Note 1 TI Note 1 TI Note 2 TI Note 2 LBE output WAIT input D0 to D15 I O UBE output Address Data Notes 1 This idle state TI is inserted by means...

Page 131: ...put HLDAK output A0 to A25 output CLKOUT input TE TH T2 TH TI Note 3 WAIT input D0 to D15 I O Row address Column address Undefined Note 2 Data Notes 1 TRPW is always inserted for 1 or more cycles 2 Th...

Page 132: ...Row address Column address Undefined Note 2 Data Notes 1 TRPW is always inserted for 1 or more cycles 2 This timing applies when in the RAS hold mode 3 This idle state TI is inserted by means of a BCC...

Page 133: ...output CLKOUT input TE TH T2 TH TI Note 3 WAIT input D0 to D15 I O Row address Column address Undefined Note 2 Data Notes 1 TRPW is always inserted for 1 or more cycles 2 This timing applies when in...

Page 134: ...m output BCYST output HLDRQ input HLDAK output A0 to A25 output CLKOUT input TB T2 TH TH TI Note 2 TI Note 2 WAIT input D0 to D15 I O Row address Column address Column address Undefined Data Data Note...

Page 135: ...TLATE TH TH TI Note 1 TI Note 1 HLDRQ input HLDAK output Note 3 output SDCKE output LDQM output UDQM output BCW Address Address Address Column address Address Data Bank address Row address Row address...

Page 136: ...HLDRQ input HLDAK output Note 4 output SDCKE output LDQM output UDQM output H BCW Address Address Address Address Bank address Row address Row address Column address Undefined Undefined Undefined Unde...

Page 137: ...HLDRQ input HLDAK output Note 3 output SDCKE output LDQM output UDQM output H Address Address Address Address Bank address Row address Row address Column address Undefined Undefined Undefined Undefine...

Page 138: ...Note 1 TI Note 1 HLDRQ input HLDAK output Note 3 output SDCKE output LDQM output UDQM output H Address Address Bank address Row address Undefined Undefined Undefined Undefined Data Data BCW Address Ad...

Page 139: ...cycle operand data access and instruction fetch in that order An instruction fetch may be inserted between a read access and write access during a read modify write access Also an instruction fetch ma...

Page 140: ...4 Burst fetch is valid only in the external memory area In memory block 7 it is terminated when the internal address count value has reached the upper limit of the external memory area 4 10 2 Data sp...

Page 141: ...o 7 states of programmable data waits can be inserted by setting the DWC0 and DWC1 registers Data wait can be controlled via WAIT pin input Up to 3 idle states can be inserted after a read write cycle...

Page 142: ...AM 1 2 a When data bus width is 8 bits A0 to A16 D1 to D8 1 Mb SRAM 128 Kwords 8 bits CS OE WE A1 to A17 D0 to D7 CSn RD LWR D8 to D15 V850E MA1 UWR A0 to A16 D1 to D8 1 Mb SRAM 128 Kwords 8 bits CS O...

Page 143: ...0 to A16 D1 to D16 2 Mb SRAM 256 Kwords 16 bits CS OE WE LBE UBE V850E MA1 A0 to A11 A12 A13 DQ0 to DQ15 64 Mb SDRAM 1 Mword 16 bits 4 banks CS LDQM UDQM WE CKE CLK RAS CAS A1 to A17 A21 A22 D0 to D15...

Page 144: ...ata WAIT input D0 to D15 I O IOWR output IORD output Note LWR LCAS output UWR UCAS output WE output OE output RD output CSn RASm output LBE output UBE output BCYST output A0 to A25 output CLKOUT outpu...

Page 145: ...dress Data WAIT input D0 to D15 I O IOWR output IORD output Note LWR LCAS output UWR UCAS output WE output OE output RD output CSn RASm output BCYST output A0 to A25 output CLKOUT output TI T2 LBE out...

Page 146: ...D15 I O IOWR output Note IORD output LWR LCAS output UWR UCAS output WE output OE output RD output BCYST output A0 to A25 output CLKOUT output Data Address TW T2 T1 CSn RASm output LBE output UBE out...

Page 147: ...Address Data WAIT input D0 to D15 I O IOWR output Note IORD output LWR LCAS output UWR UCAS output WE output OE output RD output BCYST output A0 to A25 output CLKOUT output TI T2 CSn RASm output LBE o...

Page 148: ...a WAIT input D0 to D15 I O IOWR output Note LWR LCAS output IORD output Note UWR UCAS output WE output OE output RD output BCYST output A0 to A25 output CLKOUT output T2 T1 CSn RASm output LBE output...

Page 149: ...5 I O IOWR output Note LWR LCAS output IORD output Note UWR UCAS output WE output OE output RD output BCYST output A0 to A25 output CLKOUT output T2 T1 CSn RASm output LBE output UBE output Data Addre...

Page 150: ...on to 8 bit 16 bit page ROM supported For 16 bit bus width 4 8 16 32 64 word page access supported For 8 bit bus width 8 16 32 64 128 word page access supported Page ROM is accessed in a minimum of 2...

Page 151: ...mples of Connection to Page ROM a When data bus width is 16 bits A0 to A19 O1 to O16 CE OE 16 Mb page ROM 1 Mword 16 bits A1 to A20 D0 to D15 CSn RD V850E MA1 b When data bus width is 8 bits A0 to A20...

Page 152: ...ontinuously readable bits one of the addresses A3 to A6 is set as the masking address no comparison is made Figure 5 4 On Page Off Page Judgment During Page ROM Connection 1 2 a In case of 16 Mb 1 M 1...

Page 153: ...ess A19 Off page address On page address Continuous reading possible 16 bit data bus width 8 words A6 A5 A4 A3 A2 MA6 0 MA5 0 MA4 0 MA3 1 PRC register setting Comparison c In case of 32 Mb 2 M 16 bits...

Page 154: ...e 15 0 PRC Address FFFFF49AH After reset 7000H 14 PRW2 13 PRW1 12 PRW0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 MA6 2 MA5 1 MA4 0 MA3 Bit position Bit name Function Page ROM On page Wait Control Sets the n...

Page 155: ...TW Off page address Data WAIT input D0 to D15 I O D0 to D7 I O IOWR output IORD output LWR LCAS output UWR UCAS output WE output OE output RD output CSn RASm output BCYST output A0 to A25 output CLKOU...

Page 156: ...16 bit bus width T1 TW Off page address Data WAIT input D0 to D15 I O D0 to D7 I O IOWR output IORD output LWR LCAS output UWR UCAS output WE output OE output RD output CSn RASm output BCYST output A0...

Page 157: ...rd access with 16 bit bus width TASW T1 Off page address Data WAIT input D0 to D15 I O D0 to D7 I O IOWR output IORD output LWR LCAS output UWR UCAS output WE output OE output RD output CSn RASm outpu...

Page 158: ...rd access with 16 bit bus width TASW T1 Off page address Data WAIT input D0 to D15 I O D0 to D7 I O IOWR output IORD output LWR LCAS output UWR UCAS output WE output OE output RD output CSn RASm outpu...

Page 159: ...ctly to EDO DRAM Supports the RAS hold mode 4 types of DRAM can be assigned to 4 memory block spaces Supports 2CAS type DRAM Row and column address multiplex widths can be changed Waits 0 to 3 waits c...

Page 160: ...en DRAM is 64 Mb 4 M 16 bits A0 to A11 I O1 to I O16 RAS LCAS UCAS WE OE 64 Mb DRAM 4 Mwords 16 bits A1 to A12 D0 to D15 RASn LCAS UCAS WE OE V850E MA1 b When DRAM is 16 Mb 2 M 8 bits A0 to A11 I O1 t...

Page 161: ...5 a24 a23 a25 to a18 Row address DAW1n DAW0n 10 a17 a16 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a24 a23 a22 a25 to a18 Row address DAW1n DAW0n 01 a17 a25 a21 a20 a19 a18 a17 a16 a15 a14 a1...

Page 162: ...and SCR6 registers are complete However it is possible to access external memory areas whose initialization settings are complete 1 3 15 PAE11 SCR1 Address FFFFF4A4H After reset 3FC1H 14 0 13 RPC11 1...

Page 163: ...ddress Pre charge Control Specifies the number of wait states inserted as column address precharge time CPC1n CPC0n Number of wait states inserted 0 0 0 at least 1 wait is always inserted during on pa...

Page 164: ...O0n 00B When the external data bus width is 16 bits Set ASO1n ASO0n 01B ASO1n ASO0n Address shift width 0 0 0 data bus width 8 bits 0 1 1 data bus width 16 bits 1 0 Setting prohibited 1 1 Setting proh...

Page 165: ...output UWR UCAS output WE output OE output RD output CSn RASm output BCYST output A0 to A25 output CLKOUT output TB TB T2 TE Column address Column address Column address Note 2 Notes 1 TRPW is always...

Page 166: ...put OE output RD output CSn RASm output BCYST output A0 to A25 output CLKOUT output T2 TW TRHW TB TE TW Row address Column address Column address Data Data Note 2 Notes 1 TRPW is always inserted for 1...

Page 167: ...D15 I O IOWR output IORD output LWR LCAS output UWR UCAS output WE output OE output RD output CSn RASm output BCYST output A0 to A25 output CLKOUT output T2 TW TRHW TCPWNote TW TE TI TI T1 TB Row add...

Page 168: ...OE output RD output CSn RASm output BCYST output A0 to A25 output CLKOUT output TCPWNote 1 TB T2 TCPWNote 1 TE TB Column address Column address Column address Data Data Data Data D0 to D15 I O During...

Page 169: ...WR output IORD output LWR LCAS output UWR UCAS output WE output OE output RD output CSn RASm output BCYST output A0 to A25 output CLKOUT output Column address Column address Data Note 2 Notes 1 TRPW a...

Page 170: ...RFS4 RFS6 These registers are used to enable or disable a refresh and set the refresh interval The refresh interval is determined by the following calculation formula Refresh interval s Refresh count...

Page 171: ...N46 RIN36 RIN26 RIN16 RIN06 Bit position Bit name Function 15 RENn n 1 3 4 6 Refresh Enable Specifies whether CBR refresh is enabled or disabled 0 Refresh disabled 1 Refresh enabled Refresh Count Cloc...

Page 172: ...16 124 1 24 122 9 128 fXX 39 249 6 64 248 2 250 256 fXX 19 243 2 32 248 2 48 245 8 Notes 1 The interval factor is set by bits RIN0n to RIN5n of the RFSn register n 1 3 4 6 2 The values in parentheses...

Page 173: ...0 0 1 1 1 0 2 1 1 3 7 6 RRW1 RRW0 Refresh Cycle Wait Control Specifies the number of wait states inserted as hold time for the RASm signal s low level width during CBR refresh m 1 3 4 6 RCW2 RCW1 RCW...

Page 174: ...output UWR UCAS output OE output RD output CSn RASm output BCYST output A0 to A25 output REFRQ output CLKOUT output TRCW T3 TRCWNote 1 T4 TINote 2 TINote 2 WE output Notes 1 The TRCW cycle is always i...

Page 175: ...or external device is held pending until the self refresh cycle is cleared To release the self refresh cycle use one of the three methods below 1 Release by NMI input a In the case of self refresh cy...

Page 176: ...esh cycle is started in the IDLE or software STOP mode If the self refresh cycle is started by inputting the active level of the SELFREF signal CLKOUT is output without going low 2 The TRCW cycle is a...

Page 177: ...can be inserted between the bank active command and the read write command Supports CBR refresh and CBR self refresh 5 4 2 SDRAM connection An example of connection to SDRAM is shown below Figure 5 1...

Page 178: ...19 A8 a18 A7 a17 A6 a16 A5 a15 A4 a14 A3 a13 A2 a12 A1 a11 A0 a10 a24 a23 a22 a25 to a18 Row address SAW1n SAW0n 01 a17 a25 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a23 a22 a21 a25 to a18 Ro...

Page 179: ...s output using read write command A15 a15 A14 a14 A13 a13 A25 to A18 Address pin a25 to a18 Column address SSO1n SSO0n 00 A17 a17 A16 a16 A12 a12 A11 a11 A10 0 A9 a9 A8 a8 A7 a7 A6 a6 A5 a5 A4 a4 A3 a...

Page 180: ...ween commands to write to the SCR register 1 2 15 0 SCR1 Address FFFFF4A4H After reset 0000H 14 LTM21 13 LTM11 12 LTM01 11 0 10 0 9 0 8 0 7 BCW11 6 BCW01 5 SSO11 4 SSO01 3 RAW11 2 RAW01 1 SAW11 0 SAW0...

Page 181: ...O1n SSO0n 01B SSO1n SSO0n Address shift width 0 0 8 bits 0 1 16 bits 1 0 Setting prohibited 1 1 Setting prohibited 5 4 SSO1n SSO0n n 1 3 4 6 Row Address Width Control Specifies the row address width R...

Page 182: ...ange occurs the active command and read write command for the bank to be accessed next are issued in that order Following this read write command the precharge command for the bank that was accessed b...

Page 183: ...command PR is issued before the active command The timing to sample data is synchronized with rising of the UDQM and LDQM signals A one state TW cycle is always inserted immediately before every read...

Page 184: ...Row address Address Address Bank address Address Row address SDCLK output BCYST output SDCKE output H Command SDRAS output SDCAS output CSn output WE output LDQM output UDQM output Note output Bank ad...

Page 185: ...address Address Address Row address Column address Row address Row address SDCLK output BCYST output SDCKE output H Command SDRAS output SDCAS output CSn output WE output LDQM output UDQM output Note...

Page 186: ...QM output UDQM output Note output Bank address output A10 output A0 to A9 output D0 to D15 I O On page Note Addresses other than the bank address A10 and A0 to A9 Remarks 1 The circle indicates the sa...

Page 187: ...active command ACT and write command WR are issued for SDRAM in that order During on page access however only the write command is issued and the precharge command and active command are not issued W...

Page 188: ...ut BCYST output SDCKE output H Command SDRAS output SDCAS output CSn output WE output LDQM output UDQM output Note output Address Bank address Bank address output Address Row address A10 output Addres...

Page 189: ...ddress Aaddress Address Bank address Address Bank address Address Row address Off page SDCLK output BCYST output SDCKE output H Command SDRAS output SDCAS output CSn output WE output LDQM output UDQM...

Page 190: ...dress Address Note output Column address A0 to A9 output A10 output Address Address Bank address output D0 to D15 I O Note Addresses other than the bank address A10 and A0 to A9 Remarks 1 The broken l...

Page 191: ...b Number of waits from precharge command to bank active command The number of wait states from precharge command issue to bank active command issue can be set by setting the BCW1n and BCW0n bits of t...

Page 192: ...nk address output SDRAS output SDCAS output CSn output RD output OE output WE output LDQM output UDQM output SDCKE output D0 to D15 I O H BCW BCW BCW Bank A read command Bank A read command Bank A rea...

Page 193: ...ST output Bank address output SDRAS output SDCAS output CSn output RD output OE output WE output LDQM output UDQM output SDCKE output D0 to D7 I O H Bank A read command Bank A read command Bank A read...

Page 194: ...Bank A write TWE TACT TW TWR TWR BCW Bank B write TWPRE TWE TW TW TWE TWR TWR TWPRE Bank B write Bank A write command Bank A write command Bank B write command Bank A active command Bank B active com...

Page 195: ...R TWR BCW BCW TWPRE TWE TREAD TREAD TREAD TREAD TLATE TLATE Bank B write Bank A read Bank A active command Bank A write command Bank A write command Bank A write command Bank A write command Bank A pr...

Page 196: ...4 RFS6 These registers are used to enable or disable a refresh and set the refresh interval The refresh interval is determined by the following calculation formula Refresh interval s Refresh count clo...

Page 197: ...N46 RIN36 RIN26 RIN16 RIN06 Bit position Bit name Function 15 RENn n 1 3 4 6 Refresh Enable Specifies whether CBR refresh is enabled or disabled 0 Refresh disabled 1 Refresh enabled Refresh Count Cloc...

Page 198: ...32 fXX 9 14 4 16 15 5 24 15 4 128 fXX 2 12 8 4 15 5 6 15 4 15 6 256 fXX 1 12 8 2 15 5 3 15 4 Notes 1 The interval factor is set by bits RIN0n to RIN5n of the RFSn register n 1 3 4 6 2 The values in pa...

Page 199: ...precharge command for all banks PALL is issued Figure 5 17 Auto Refresh Cycle TREFW PALL REF TABPW TREFW TREFW TREF H H Address Auto refresh cycle SDCLK output BCYST output SDCKE output H H Command SD...

Page 200: ...tput CSn output BCYST output A0 to A9 A11 to A23 output A10 output SDCLK output ALLPRE TW TW TREF TBCW TBCW TW TBCW TBCW TBCW TBCW TBCW TBCW TI TI SDCKE output LDQM output UDQM output All bank prechar...

Page 201: ...le However access to an on chip peripheral I O register or external device is held pending until the self refresh cycle is cleared To release the self refresh cycle use one of the three methods below...

Page 202: ...CW TDCW TDCW SDCKE output LDQM output UDQM output All bank precharge command Refresh command NOP command H H BCW 4clk Note Note Shown above is the case when the self refresh cycle is started in the ID...

Page 203: ...When writing data to these registers the following commands are issued for SDRAM in the order shown below All bank precharge command Refresh command 8 times Command that is used to set a mode register...

Page 204: ...S TABPW TREFW TREFW TREF MD MD H H Mode register setting cycle Refresh command REF generated 8 times SDCLK output BCYST output SDCKE output H H Command SDRAS output SDCAS output CSn output WE output L...

Page 205: ...AS output SDRAS output CSn output BCYST output A0 to A9 output A10 output Bank address output Note output SDCLK output SDCKE output H LDQM output UDQM output SCRn register write All bank precharge com...

Page 206: ...rs memory refers to internal RAM or external memory 6 1 Features 4 independent DMA channels Transfer unit 8 16 bits Maximum transfer count 65 536 2 16 Two types of transfer Flyby 1 cycle transfer 2 cy...

Page 207: ...V850E MA1 Bus interface External bus External RAM External ROM External I O DMA source address register DSAnH DSAnL DMA transfer count register DBCn DMA channel control register DCHCn DMA terminal cou...

Page 208: ...units Caution When setting an address of a peripheral I O register for the source address be sure to specify an address between FFFF000H and FFFFFFFH An address of the peripheral I O register image 3...

Page 209: ...0 SA0 SA15 DSA1L FFFFF088H Undefined SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SA15 DSA2L FFFFF090H Undefined SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 S...

Page 210: ...eripheral I O register for the destination address be sure to specify an address between FFFF000H and FFFFFFFH An address of the peripheral I O register image 3FFF000H to 3FFFFFFH must not be specifie...

Page 211: ...A1 0 DA0 DA15 DDA1L FFFFF08CH Undefined DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA15 DDA2L FFFFF094H Undefined DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0...

Page 212: ...rwritten the value set immediately before the DMA transfer will be read out 0000H will not be read even if DMA transfer has ended 15 BC15 DBC0 Address FFFFF0C0H After reset Undefined 14 BC14 13 BC13 1...

Page 213: ...4H 0000H DS0 0 0 0 0 0 0 SAD1 SAD0 DAD1 DAD0 TM1 TM0 TTYP TDIR DS1 DADC3 FFFFF0D6H 0000H DS0 0 0 0 0 0 0 SAD1 SAD0 DAD1 DAD0 TM1 TM0 TTYP TDIR Bit position Bit name Function Data Size Sets the transfe...

Page 214: ...ansfer mode 0 1 Single step transfer mode 1 0 Setting prohibited 1 1 Block transfer mode 3 2 TM1 TM0 1 TTYP Transfer Type Sets the DMA transfer type 0 2 cycle transfer 1 Flyby transfer 0 TDIR Transfer...

Page 215: ...unt output the Enn bit is not cleared to 0 and the DMA transfer enable state is retained Moreover the next DMA transfer request can be acknowledged even when the TCn bit is not read When this bit is c...

Page 216: ...errupted by NMI input The ENn bit of this register and the Enn bit of the DCHCn register are linked to each other n 0 to 3 Following forcible interrupt by NMI input the DMA channel that was interrupte...

Page 217: ...be read written in 8 or 1 bit units Address FFFFF8A0H 7 0 DTOC 6 0 5 0 4 0 3 TCO3 2 TCO2 1 TCO1 0 TCO0 After reset 01H Bit position Bit name Function 3 to 0 TCO3 to TCO0 Terminal Count Output Indicate...

Page 218: ...0 00H Bit position Bit name Function 7 DFn DMA Request Flag This is a DMA transfer request flag Only 0 can be written to this flag 0 DMA transfer not requested 1 DMA transfer requested If the interrup...

Page 219: ...1 1 1 INTP112 0 1 0 0 0 0 INTP113 0 1 0 0 0 1 INTP120 0 1 0 0 1 0 INTP121 0 1 0 0 1 1 INTP122 0 1 0 1 0 0 INTP123 0 1 0 1 0 1 INTP130 0 1 0 1 1 0 INTP131 0 1 0 1 1 1 INTP132 0 1 1 0 0 0 INTP133 0 1 1...

Page 220: ...n 0 to 3 DMARQn IFCn0 to IFCn5 Internal DMA request signal Interrupt source Selector Remark If an interrupt request is specified as the DMA transfer start factor an interrupt request will be generate...

Page 221: ...R state The T2R state corresponds to the last state of a read operation in the 2 cycle transfer mode or to a wait state In the last T2R state read data is sampled After entering the last T2R state the...

Page 222: ...state 12 T2FH state The T2FH state is the state during which it is judged whether flyby transfer is to be continued or not If the next transfer is executed in the block transfer mode the bus enters t...

Page 223: ...state transition Except for the block transfer mode each time the processing for a DMA transfer is completed the bus mastership is released Figure 6 1 DMAC Bus Cycle State Transition a 2 cycle transf...

Page 224: ...remains active DMA transfer with the lower priority newly request is executed after the CPU bus has been released Figures 6 2 to 6 5 show examples of single transfer Figure 6 2 Single Transfer Example...

Page 225: ...Note Note Note Note Note Note Note The bus is always released Figure 6 5 is an example of single transfer where two or more DMA transfer requests with the lower priority are issued one clock after si...

Page 226: ...e The following shows an example of a single step transfer Figure 6 7 shows an example of single step transfer made in which a higher priority DMA request is issued DMA channels 0 and 1 are in the sin...

Page 227: ...releases the bus another DMA transfer can be acknowledged The bus cycle of the CPU is not inserted during block transfer but bus hold and refresh cycles are inserted in between DMA transfer operations...

Page 228: ...ansfer data transfer is performed in two cycles a read cycle source to DMAC and a write cycle DMAC to destination In the first cycle the source address is output and reading is performed from the sour...

Page 229: ...to A25 output D0 to D15 I O DMARQx input CLKOUT output BCYST output CSn RASm output of SRAM area CSn RASm output of external I O area OE output RD output IORD output IOWR output WAIT input WE output...

Page 230: ...utput CSn RASm output of SRAM area CSn RASm output of external I O area OE output RD output IORD output IOWR output WAIT input WE output DMAAKx output TCx output LBE output UBE output LWR LCAS output...

Page 231: ...DMA request signal DMARQx input CLKOUT output BCYST output TCx output CSm output of external I O area OE output RD output IORD output Note 2 IOWR output Note 2 WAIT input WE output Data Data H H DMAAK...

Page 232: ...TO T1R T1W T2W T2W T2R TI TI T1 T2 T1 TI TI T1 TI T2 TO T2 T1 T2 TRPW Note 2 Note 2 T1W TCPW Note 3 Note 4 T2W TB T2 T1 T2 TE TW TI TW Data Data Data Address TE TI T1 T1R T1 T2R T2 Data Data Data Data...

Page 233: ...W Note 3 Note 4 T2W TB T2 T1 T2 TE Data Data Data Address TE TI T1 T1R T1 T2R T2 Data Data Data Data RASm output of DRAM area CSn output of other area CSn output of SRAM area Note 2 Note 2 Note 1 Note...

Page 234: ...Note 4 T2W TB T2 T1 T2 TE Data Data Data Address TE T1R T1 T2R T2 Data Data Note 2 Note 2 RASm output of DRAM area CSn output of other area CSn output of SRAM area Note 1 Note 1 Row Col Col Notes 1 T...

Page 235: ...D15 I O Address Data TI TI TI TI TO T1R T2R T2R T1 T2 T1 T1W TI T1 T2W T2 TO T2 TI T2 T2 TRPW Note 2 T1 T2 TE TW TI TW Data Data Data Data Address TE TI T1 TI T1 T1R TB T2W T2 T1W T1 Data Data Data R...

Page 236: ...ut D0 to D15 I O Address Data TI TI TI TI TO T1R T2R T2R T1 T2 T1 T1W T1 T2W T2 TI T2 TI T2 T2 TRPW Note 2 T1 T2 TE Data Data Data Data Address TE TI T1 TI T1 T1R TB T2W T2 T1W T1 Data Data Data RASm...

Page 237: ...Data TI TI TI TI TO T1R T2R T2R T1 T2 T1 T1W T1 T2W T2 T2 TRPW Note 3 T1 T2 TE Data Data Data Data Address TE TI T1R TB T2W T2 T1W T1 Data RASm output of DRAM area CSn output of other area CSn output...

Page 238: ...Address Col Col Data H TI TI TI TI TO T1R T1W T2W T2W T2R TI TI T1 T2 T1 TI TI T1 TI T2 TO T2 T1 T2 TW T1W TW T2 TACT TWR T2W TWR TWE TW TI TW TWPRE Data Data Data Address T2W T2W TWE TWPRE T2W T2W T...

Page 239: ...o D15 I O Address Col Col Data H TI TI TI TI TO T1R T1W T2W T2W T2R TI TI T1 T2 T1 TI T1 TI T2 TI T2 T1 T2 TW T1W TW T2 TACT TWR T2W TWR TWE TWPRE Data Data Data Address T2W T2W TWE TWPRE T2W T2W TI T...

Page 240: ...utput D0 to D15 I O Address Col Col Data H TI TI TI TI TO T1R T1W T2W T2W T2R TI TI TI T1 T2 T1 T1 T2 TW T1W TW T2 TACT TWR T2W TWR TWE TWPRE Data Data Data Address T2W T2W TWE TWPRE T2W T2W T1R T1 T2...

Page 241: ...Address Col Col H TI TI TI TI TO T1R T2R TI TI T1 T2 T1 TI TI T1 T1 TI T2 T2 TO T2 T2 TW T1W TW TACT TW TI TW Data Data Address T1W TREAD T2R TLATE T2R TLATE T2R TREAD T2W TLATE T2W TLATE T2W T2W T1R...

Page 242: ...I TI TI TO T1R T2R TI TI T1 T2 T1 TI T1 T1 TI T2 T2 TI T2 T2 TW T1W TW TACT Data Data Address T1W TREAD T2R TLATE T2R TLATE T2R TREAD T2W TLATE T2W TLATE T2W T2W T1R T2R TI T1 T2 T1 Data Data Data Dat...

Page 243: ...Col H TI TI TI TI TO T1R T2R TI TI TI T1 T2 T1 T1 T2 T2 TW T1W TW TACT Data Data Address T1W TREAD T2R TLATE T2R TLATE T2R TREAD T2W TLATE T2W TLATE T2W T2W T1R T2R T2 T1 Data Data Data Data CSn outpu...

Page 244: ...als To perform a normal access to the external I O by means other than DMA transfer externally AND the CSm and DMAAKx signals m 0 to 7 x 0 to 3 and connect the resultant signal to the chip select sign...

Page 245: ...put BCYST output RASm output of DRAM area CSn output of external I O area OE output RD output IORD output IOWR output WAIT input WE output Internal DMA request signal DMAAKx output TCx output LWR LCAS...

Page 246: ...to D15 I O A0 to A25 output Internal DMA request signal DMARQx input CLKOUT output BCYST output TCx output RASm output of DRAM area OE output RD output IORD output IOWR output WAIT input WE output Da...

Page 247: ...I O A0 to A25 output Internal DMA request signal DMARQx input CLKOUT output BCYST output TCx output RASm output of DRAM area OE output RD output IORD output IOWR output WAIT input WE output DMAAKx out...

Page 248: ...T input D0 to D15 I O IOWR output IORD output LWR LCAS LDQM output UWR UCAS UDQM output WE output OE output RD output CSn RASm output BCYST output A0 to A25 output CLKOUT output TF TI T2 When TASW and...

Page 249: ...CAS LDQM output UWR UCAS UDQM output WE output OE output RD output CSn RASm output BCYST output A0 to A25 output CLKOUT output TF T1 T2 When TASW is inserted TW TF T2 DMAAKx output Address Data LBE ou...

Page 250: ...IT input D0 to D15 I O IOWR output IORD output LWR LCAS output UWR UCAS output WE output OE output RD output CSn RASm output BCYST output A0 to A25 output CLKOUT output TI T1 TF TW TF T2 DMAAKx output...

Page 251: ...ut TF TE T2 TB TE TF DMAAKx output Column address Data Note 4 Note 4 Note 4 Note 4 Note 3 Notes 1 TRPW is always inserted for one or more cycles 2 During DMA flyby transfer the rise timing of this rea...

Page 252: ...3 TCPW Note 1 TE TO1 TW TE TO2 DMAAKx output Column address Data Note 3 Note 4 Note 4 Note 4 Note 4 Notes 1 TRPW and TCPW are always inserted for one or more cycles 2 During DMA flyby transfer the ris...

Page 253: ...CPWNote 1 T2 TB TE DMAAKx output Column address Data Note 4 Note 4 Note 4 Note 4 Note 3 Notes 1 TRPW and TCPW are always inserted for one or more cycles 2 During DMA flyby transfer the rise timing of...

Page 254: ...1 TE TW DMAAKx output Column address Data IORDNote 2 output Note 4 Note 4 Note 4 Note 4 Note 3 Notes 1 TRPW and TCPW are always inserted for one or more cycles 2 During DMA flyby transfer the rise tim...

Page 255: ...FH cannot be specified for the source and destination address of DMA transfer Be sure to specify an address between FFFF000H and FFFFFFFH Remarks 1 During 2 cycle DMA transfer if the data bus width of...

Page 256: ...by the BCT register Note Other external cycles such as a CPU based bus cycle can be started 6 8 DMA Channel Priorities The DMA channel priorities are fixed as follows DMA channel 0 DMA channel 1 DMA...

Page 257: ...e automatically rewritten with the value that was set immediately before Therefore during DMA transfer transfer is automatically started when a new DMA transfer setting is made for these registers and...

Page 258: ...gnal becomes active in the TI state it changes to the T0 state and DMA transfer is started 2 Request from software If the STGn Enn and TCn bits of the DCHCn register are set as follows DMA transfer st...

Page 259: ...errupted by NMI input during DMA transfer At such a time the DMAC resets the Enn bit of the DCHCn register of all channels to 0 and the DMA transfer disabled state is entered An NMI request can then b...

Page 260: ...ADC2 DCHC2 Register set DCHC2 INIT2 bit 1 Register set DSA3 DDA3 DBC3 DADC3 DCHC3 Register set E22 bit 1 TC2 bit 0 E22 bit 0 TC2 bit 0 E33 bit 1 TC3 bit 0 E33 bit 0 TC3 bit 1 b When transfer is aborte...

Page 261: ...ternal RAM access 1 clock Remark n 0 to 3 6 15 Maximum Response Time for DMA Transfer Request The response time for a DMA transfer request becomes the longest under the following conditions in the DRA...

Page 262: ...sfer During Single Transfer via DMARQ0 to DMARQ3 Signals The DMARQn signal is sampled at the rising edge of the third clock after the cycle of DMA transfer in the single transfer mode has been complet...

Page 263: ...can access the internal ROM 4 DMAAKn signal output When the transfer object is internal RAM the DMAAKn signal is not output during a DMA cycle for internal RAM for example if 2 cycle transfer is perfo...

Page 264: ...ver exception processing can be started by the TRAP instruction software exception or by generation of an exception event i e fetching of an illegal opcode exception trap 7 1 Features Interrupts Non m...

Page 265: ...f INTP020 pin CCC20 Pin RPU 8 0100H 00000100H nextPC Interrupt INTP021 INTM021 P02IC1 Match of INTP021 pin CCC21 Pin RPU 9 0110H 00000110H nextPC Interrupt INTP030 INTM030 P03IC0 Match of INTP030 pin...

Page 266: ...SIO 40 0300H 00000300H nextPC Interrupt INTSER1 SEIC1 UART1 reception error SIO 41 0310H 00000310H nextPC Interrupt INTSR1 SRIC1 UART1 reception completion SIO 42 0320H 00000320H nextPC Interrupt INT...

Page 267: ...ter 0 INTM0 is detected at the NMI pin the interrupt occurs While the service program of the non maskable interrupt is being executed PSW NP 1 the acknowledgement of another non maskable interrupt req...

Page 268: ...rd FECC of ECR 4 Sets the NP and ID bits of the PSW and clears the EP bit 5 Sets the handler address 00000010H corresponding to the non maskable interrupt to the PC and transfers control The servicing...

Page 269: ...equest PSW NP 1 NMI request is held pending regardless of the value of the NP bit of PSW Pending NMI request serviced b If a new NMI request is generated twice while an NMI service program is being ex...

Page 270: ...is 1 2 Transfers control back to the address of the restored PC and PSW Figure 7 3 illustrates how the RETI instruction is processed Figure 7 3 RETI Instruction Processing PSW EP RETI instruction PSW...

Page 271: ...interrupt servicing is in progress 0 No NMI interrupt servicing 1 NMI interrupt currently being serviced 7 2 4 Noise elimination NMI pin noise is eliminated with analog delay The delay time is 60 to...

Page 272: ...g a higher priority than the interrupt request in progress specified by the interrupt control register Note that only interrupts with a higher priority will have this capability interrupts with the sa...

Page 273: ...her interrupt request Highest default priority of interrupt requests with the same priority EIPC EIPSW ECR EICC PSW EP PSW ID Corresponding bit of ISPRNote PC Restored PC PSW Exception code 0 1 1 Hand...

Page 274: ...d PSW Figure 7 5 illustrates the processing of the RETI instruction Figure 7 5 RETI Instruction Processing Note For the ISPR register see 7 3 6 In service priority register ISPR Caution When the PSW E...

Page 275: ...specified by the xxPRn bit are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level beforehand F...

Page 276: ...igher than that of c d is held pending because interrupts are disabled Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e Interrupt request...

Page 277: ...t j is held pending because its priority is lower than that of i k that occurs after j is acknowledged because it has the higher priority Interrupt requests m and n are held pending because servicing...

Page 278: ...vicing of interrupt request c Servicing of interrupt request a Interrupt request b and c are acknowledged first according to their priorities Because the priorities of b and c are the same b is acknow...

Page 279: ...issued The flag xxlFn is reset automatically by the hardware if an interrupt request is acknowledged 6 xxMKn Mask Flag This is an interrupt mask flag 0 Interrupt servicing enabled 1 Interrupt servicin...

Page 280: ...31 P10PR30 FFFFF130H P11IC0 P11IF0 P11MK0 0 0 0 P11PR02 P11PR01 P11PR00 FFFFF132H P11IC1 P11IF1 P11MK1 0 0 0 P11PR12 P11PR11 P11PR10 FFFFF134H P11IC2 P11IF2 P11MK2 0 0 0 P11PR22 P11PR21 P11PR20 FFFFF1...

Page 281: ...160H CSIIC1 CSIIF1 CSIMK1 0 0 0 CSIPR12 CSIPR11 CSIPR10 FFFFF162H SEIC1 SEIF1 SEMK1 0 0 0 SEPR12 SEPR11 SEPR10 FFFFF164H SRIC1 SRIF1 SRMK1 0 0 0 SRPR12 SRPR11 SRPR10 FFFFF166H STIC1 STIF1 STMK1 0 0 0...

Page 282: ...ter instead of the IMRm register are rewritten as a result the contents of the IMRm register are also rewritten Address FFFFF100H 15 P10MK3 IMR0 14 P10MK2 13 P10MK1 12 P10MK0 11 P03MK1 10 P03MK0 9 P02...

Page 283: ...ty n not acknowledged 1 Interrupt request with priority n acknowledged Remark n 0 to 7 priority level 7 3 7 Maskable interrupt status flag ID The ID flag is bit 5 of the PSW and controls the maskable...

Page 284: ...by external interrupt mode registers 1 to 4 INTM1 to INTM4 1 External interrupt mode registers 1 to 4 INTM1 to INTM4 These registers specify the trigger mode for external interrupt requests INTP100 to...

Page 285: ...7 to 0 ES1nm1 ES1nm0 n 0 to 3 m 0 to 3 Notes 1 The level of the INTP1nm pin is sampled at the interval of the system clock divided by two and the P1nIFm bit is latched as an interrupt request when a l...

Page 286: ...10 INTP011 SESC2 TI020 INTP020 INTP021 SESC3 TI030 INTP030 INTP031 The valid edge can be specified independently for each pin rising edge falling edge or both rising and falling edges These registers...

Page 287: ...reset 00H TES31 TES30 0 0 IES0311 IES0310 IES0301 IES0300 TES11 TES10 0 0 IES0111 IES0110 IES0101 IES0100 TES21 TES20 0 0 IES0211 IES0210 IES0201 IES0200 TI000 INTP001 INTP000 TI010 INTP011 INTP010 TI...

Page 288: ...nterrupt source 4 Sets the EP and ID bits of the PSW 5 Sets the handler address 00000040H or 00000050H corresponding to the software exception to the PC and transfers control Figure 7 8 illustrates th...

Page 289: ...to the address of the restored PC and PSW Figure 7 9 illustrates the processing of the RETI instruction Figure 7 9 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Origina...

Page 290: ...indicate that exception processing is in progress It is set when an exception occurs 31 0 PSW After reset 00000020H 7 NP 6 EP 5 ID 4 SAT 3 CY 2 OV 1 S Z 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 291: ...tion trap is generated when an instruction applicable to this illegal instruction is executed 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to Arbitrary Caution Since it is possible t...

Page 292: ...tion trap is carried out by the DBRET instruction By executing the DBRET instruction the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC an...

Page 293: ...performs the following processing 1 Operation 1 Saves the restored PC to DBPC 2 Saves the current PSW to DBPSW 3 Sets the NP EP and ID bits of the PSW 4 Sets the handler address 00000060H correspondi...

Page 294: ...on the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the rest...

Page 295: ...maskable interrupts is executed when interrupts are enabled ID 0 Thus to execute multiple interrupts it is necessary to set the interrupt enabled state ID 0 even for an interrupt service routine If m...

Page 296: ...t control request register xxlCn provided for each maskable interrupt request After system reset an interrupt request is masked by the xxMKn bit and the priority order is set to level 7 by the xxPRn0...

Page 297: ...D EX INT1 INT2 INT3 INT4 Note For interleave access refer to 8 1 2 2 clock branch in V850E1 User s Manual Architecture U14559E Remark INT1 to INT4 Interrupt acknowledgement processing IFX Invalid inst...

Page 298: ...LDSR reg2 0x5 instruction for PSW The store instruction for the command register PRCMD The load store or bit manipulation instructions for the following registers Interrupt related registers Interrupt...

Page 299: ...ock and supplies the divided clock to internal peripheral units The divided clock differs depending on the unit For the timer units and A D converter a 2 division clock is input For other units the in...

Page 300: ...Features Multiplication function using phase locked loop PLL synthesizer Clock sources Oscillation by connecting a resonator External clock Power save control HALT mode IDLE mode Software STOP mode I...

Page 301: ...modes are provided for the clock generator These are PLL mode and direct mode The operation mode is selected by the CKSEL pin The input to this pin is latched on reset CKSEL Operating Mode 0 PLL mode...

Page 302: ...de only an fX 4 to 5 MHz value for which 10 fX does not exceed the system clock maximum frequency 50 MHz can be used for the oscillation frequency or external clock frequency However if any of 5 fX 2...

Page 303: ...ifies the functions of the X1 and X2 pins 0 A resonator is connected to the X1 and X2 pins 1 An external clock is connected to the X1 pin When CESEL 1 the oscillator feedback loop is disconnected to p...

Page 304: ...returned to PSW No special sequence is required to read the specific register Cautions 1 If an interrupt is acknowledged between the issuance of data to the PHCMD 3 and writing to the specific regist...

Page 305: ...t units 7 6 5 4 3 2 1 0 Address After reset PHS 0 0 0 0 0 0 0 PRERR FFFFF802H 00H Bit position Bit name Function 0 PRERR Protection Error 0 Protection error has not occurred 1 Protection error occurre...

Page 306: ...ock Status Flag This is a read only flag that indicates the PLL lock state This flag holds the value 0 as long as a lockup state is maintained and is not initialized by a system reset 0 Indicates that...

Page 307: ...e STOP mode and HALT mode in relation to the clock stabilization time and current consumption It is used for situations in which a low current consumption mode is to be used and the clock stabilizatio...

Page 308: ...Note Set HALT mode Release according to RESET NMI or maskable interrupt HALT mode Release according to RESET NMI or maskable interruptNote Note INTP1nn n 0 to 3 When level detection is specified for t...

Page 309: ...oftware STOP mode 2 Command register PRCMD This is an 8 bit register that is used to set protection for write operations to registers that can significantly affect the system so that the application s...

Page 310: ...enable disable setting for standby mode release using an unmasked maskable interrupt INTP1nn n 0 to 3 0 Release by maskable interrupt enabled 1 Release by maskable interrupt disabled 1 STB Standby Mod...

Page 311: ...n assumption that 3 and 4 above are executed by the program with consecutive store instructions If another instruction is set between 3 and 4 the above sequence may become ineffective when the interru...

Page 312: ...continues for all on chip peripheral I O units other than ports that do not depend on CPU instruction processing Table 9 2 shows the status of each hardware unit in HALT mode Caution If the HALT inst...

Page 313: ...the interrupt request that is currently being serviced HALT mode is released but the newly generated interrupt request is not acknowledged The new interrupt request is held pending ii If an interrupt...

Page 314: ...illation stabilization time or the PLL lockup time does not need to be secured The system is switched to IDLE mode by setting the PSC or PSMR register using a store instruction ST or SST instruction o...

Page 315: ...ports Stopped Internal data All internal data such as CPU registers statuses data and the contents of internal RAM are maintained in the state they were in immediately before IDLE mode began D0 to D15...

Page 316: ...quest that is currently being serviced IDLE mode is released and the newly generated interrupt request is acknowledged Table 9 5 Operation After IDLE Mode Is Released by Interrupt Request Release Sour...

Page 317: ...5 2 Control registers When PLL mode and resonator connection mode CESEL bit of CKC register 0 are used the oscillator s oscillation stabilization time must be secured after software STOP mode is rele...

Page 318: ...M are maintained in the state they were in immediately before software STOP mode began D0 to D15 A0 to A25 High impedance RD WE OE BCYST UWR LWR IORD IOWR LDQM UDQM CS0 to CS7 High level output LCAS U...

Page 319: ...new interrupt request is held pending ii If an interrupt request including non maskable interrupt requests is generated with a higher priority than that of the interrupt request that is currently bei...

Page 320: ...clock output begins and processing branches to the NMI interrupt or maskable interrupt INTP1nn handler address Oscillation waveform X2 Set software STOP mode Oscillator is stopped CLKOUT output Inter...

Page 321: ...izes is secured according to the low level width of the signal that is input to the pin The supply of internal system clocks begins after a rising edge is input to the RESET pin and processing branche...

Page 322: ...it of CKC register 0 the TBC counts the oscillation stabilization time after software STOP mode is released and program execution begins after the count is completed The TBC count clock is selected ac...

Page 323: ...iew timer C 16 bit timer counter Capture compare common registers 8 Interrupt request sources Capture match interrupt requests 8 Overflow interrupt requests 4 Timer counter count clock sources 2 Selec...

Page 324: ...onversion start trigger CCC11 Read write INTM011 INTP011 TO01 R A D conversion start trigger TMC2 Read INTOV02 CCC20 Read write INTM020 INTP020 TO02 S CCC21 Read write INTM021 INTP021 TO02 R TMC3 Read...

Page 325: ...0 FFFFF600H 0000H Address After reset 0 TMC3 FFFFF630H 0000H TMCn performs the count up operations of an internal count clock or external count clock Timer start and stop are controlled by the TMCCEn...

Page 326: ...fXX 64 fXX 128 fXX 256 and fXX 512 by the TMCCn0 register fXX internal system clock An overflow interrupt can be generated if the timer overflows Also the timer can be stopped following an overflow b...

Page 327: ...tected as capture triggers The timer TMCn is synchronized with the capture trigger and the value of TMCn is latched in the CCCn0 and CCCn1 registers capture operation The valid edge of the INTP0n0 pin...

Page 328: ...reset function The corresponding timer output TO0n is set or reset in synchronization with the generation of a match signal n 0 to 3 The interrupt selection source differs according to the function o...

Page 329: ...CAE1 FFFFF616H 00H TMCC20 OVF2 CS22 CS21 CS20 0 0 TMCCE2 TMCCAE2 FFFFF626H 00H TMCC30 OVF3 CS32 CS31 CS30 0 0 TMCCE3 TMCCAE3 FFFFF636H 00H Bit position Bit name Function 7 OVFn n 0 to 3 Overflow This...

Page 330: ...Controls the operation of TMCn n 0 to 3 0 Count disabled stops at 0000H and does not operate 1 Counting operation is performed Caution When TMCCEn 0 the external pulse output TO0n becomes inactive th...

Page 331: ...n 0 to 3 1 2 7 6 5 4 3 2 1 0 Address After reset TMCC01 OST0 ENT01 ACTLV0 ETI0 CCLR0 0 CMS01 CMS00 FFFFF608H 20H TMCC11 OST1 ENT11 ACTLV1 ETI1 CCLR1 0 CMS11 CMS10 FFFFF618H 20H TMCC21 OST2 ENT21 ACTLV...

Page 332: ...MCn match during a compare operation TMCn is cleared 1 CMSn1 n 0 to 3 Capture Compare Mode Select Selects the operation mode of the capture compare register CCCn1 n 0 to 3 0 The register operates as a...

Page 333: ...g the TMCCEn bit of the TMCCn0 register to 0 If the SESCn register is overwritten during timer operation operation cannot be guaranteed 7 6 5 4 3 2 1 0 Address After reset SESC0 TES01 TES00 0 0 IES001...

Page 334: ...mer output signal TO0n can be set or reset Also a capture operation that holds the TMCn count value in the CCCn0 or CCCn1 register is performed in synchronization with the valid edge that was detected...

Page 335: ...Also the overflow interrupt INTOV0n is not generated When the TMCn register is changed from FFFFH to 0000H because the TMCCEn bit changes from 1 to 0 the TMCn register is considered to be cleared but...

Page 336: ...sed as an external trigger capture trigger The TMCn count value during counting is captured and held in the capture register in synchronization with that capture trigger signal The capture register va...

Page 337: ...s Manual U14359EJ4V0UM 337 Figure 10 4 TMC1 Capture Operation Example When Both Edges Are Specified TMC1 Count start TMCCE1 1 Overflow OVF1 1 D0 D1 D2 D0 D1 D2 Interrupt request INTP011 TMC1 count val...

Page 338: ...signal causes the timer output pin TO0n to change and an interrupt request signal INTM0n0 or INTM0n1 to be generated at the same time If the CCCn0 or CCCn1 registers are set to 0000H the 0000H after t...

Page 339: ...339 Figure 10 5 Compare Operation Example 2 2 b When CCLR0 1 and CCC00 is 0000H 0001H 0000H 0000H 0000H FFFFH TMC0 INTOV00 Count up Compare register CCC00 Match detection INTM000 Remark The match is d...

Page 340: ...TO0n pin is reset The output level of the TO0n pin can be specified by the TMCCn1 register Remark n 0 to 3 Table 10 2 TO0n Output Control TO0n Output ENTn1 ACTLVn External Pulse Output Output Level 0...

Page 341: ...Cn0 register the TMCn register is cleared 0000H and an interrupt request signal INTM0n0 is generated at the same time that the count operation resumes Remark n 0 to 3 Figure 10 7 Contents of Register...

Page 342: ...Operation Timing Example 0000H 0001H p 0000H 0001H p p p p p p 0000H 0001H t Count start Interval time Interval time Interval time Count clock TMCn register CCCn0 register INTM0n0 interrupt Clear Cle...

Page 343: ...s counting In this way a PWM signal whose frequency is determined according to the setting of the CSn2 to CSn0 bits of the TMCCn0 register can be output When the setting value of the CCCn0 register an...

Page 344: ...H Count clock TMCn register CCCn0 register CCCn1 register INTM0n0 interrupt INTM0n1 interrupt TO0n output Count start Clear t Remarks 1 p Setting value of CCCn0 register 0000H to FFFFH q Setting value...

Page 345: ...of the INTP0n1 pin is set as the trigger for capturing the TMCn register value in the CCCn1 register When this value is captured an INTM0n1 interrupt is generated The cycle of signals input to the IN...

Page 346: ...e count operation 0 0 1 0 1 0 1 0 1 0 0 0 OSTn ENTn1 ACTLVn ETIn CCLRn CMSn1 CMSn0 0 1 0 1 0 1 0 1 0 0 1 1 OVFn TMCCn0 TMCCn1 CSn2 CSn1 CSn0 TMCCEnTMCCAEn Use CCCn0 register as capture register when m...

Page 347: ...D0 t D3 D2 t 10000H D1 D2 tNote t Count clock TMCn register INTP0n0 input CCCn0 register INTM0n0 interrupt INTOV0n interrupt No overflow Overflow occurs No overflow Clear Count start Note When an over...

Page 348: ...TMCCAEn bit 5 The analog noise elimination time two cycles of the input clock are required to detect the valid edge of the external interrupt request signal INTP0n0 or INTP0n1 or the external clock i...

Page 349: ...le 10 3 Timer D Configuration Timer Count Clock Register Read Write Generated Interrupt Signal Capture Trigger Timer Output S R Other Functions TMD0 Read CMD0 Read write INTCMD0 TMD1 Read CMD1 Read wr...

Page 350: ...TMDCAEn bit 0 TMDCEn bit 0 Match of TMDn register and CMDn register Overflow Cautions 1 If the TMDCAEn bit of the TMCDn register is cleared 0 a reset is performed asynchronously 2 If the TMDCEn bit o...

Page 351: ...ster is read data in the master side is read out CMDn can be read or written in 16 bit units Cautions 1 A write operation to a CMDn register requires 4 clocks until the value that was set in the CMDn...

Page 352: ...ample of Timing During TMDn Operation a When TMDn CMDn TMDn TMDCAEn TMDCEn CMDn INTCMDn M N N N Remark M TMDn value when overwritten N CMDn value when overwritten M N b When TMDn CMDn TMDn TMDCAEn TMD...

Page 353: ...MCD3 0 CS32 CS31 CS30 0 0 TMDCE3 TMDCAE3 FFFFF574H 00H Bit position Bit name Function Count Enable Select Selects the TMDn internal count clock cycle n 0 to 3 CSn2 CSn1 CSn0 Count cycle 0 0 0 fXX 4 0...

Page 354: ...of input clocks to the TMDn unit stops 1 Input clocks are supplied to the TMDn unit Cautions 1 When the TMDCAEn bit is set to 0 the TMDn unit can be asynchronously reset 2 When TMDCAEn 0 the TMDn uni...

Page 355: ...the interrupt causes TMDn to be cleared 0 at the next count timing This function enables timer D to be used as an interval timer CMDn can also be set to 0 In this case when an overflow occurs and TMDn...

Page 356: ...UNIT 356 User s Manual U14359EJ4V0UM Figure 10 14 TMD0 Compare Operation Example 2 2 b When CMD0 is set to 0 1 0 0 0 FFFFH Overflow TMD0 Count clock CMD0 TMD0 clear Match detected INTCMD0 Count up Cle...

Page 357: ...nternal units When a count operation begins the count cycle from 0000H to 0001H differs from subsequent cycles 3 To initialize the TMDn register status and start counting again clear 0 the TMDCEn bit...

Page 358: ...e performed CSI0 to CSI2 transfer data according to three types of signals 3 wire serial I O These signals are the serial clock SCK0 to SCK2 serial input SI0 to SI2 and serial output SO0 to SO2 signal...

Page 359: ...rror interrupt INTSERn Interrupt is generated according to the logical OR of the three types of reception errors Reception completion interrupt INTSRn Interrupt is generated when receive data is trans...

Page 360: ...s of TXBn data and the transmit shift register data flag which indicates whether transmission is in progress 4 Reception control parity check Receive operations are controlled according to the content...

Page 361: ...ontrol parity Transmit operations are controlled by adding a start bit parity bit or stop bit to the data that is written to the TXBn register according to the contents that were set in the ASIMn regi...

Page 362: ...to UARTn unit 1 Supplies clocks to UARTn unit Cautions 1 When the UARTCAEn bit is set to 0 the UARTn unit can be asynchronously reset 2 When UARTCAEn 0 the UARTn unit is in a reset state Therefore to...

Page 363: ...ent is made Therefore no error interrupt is generated because the PEn bit of the ASISn register is not set Even parity If the transmit data contains an odd number of bits with the value 1 the parity b...

Page 364: ...on error interrupt request INTSERn is generated when an error occurs In this case no reception completion interrupt request INTSRn is generated 1 A reception completion interrupt request INTSRn is gen...

Page 365: ...E1 FFFFFA13H 00H ASIS2 0 0 0 0 0 PE2 FE2 OVE2 FFFFFA23H 00H Bit position Bit name Function 2 PEn n 0 to 2 Parity Error This is a status flag that indicates a parity error 0 When the UARTCAEn and RXEn...

Page 366: ...a transmit buffer data flag 0 No data to be transferred next exists in the TXBn register when the UARTCAEn or TXEn bit of the ASIMn register is cleared to 0 or when data has been transferred to the tr...

Page 367: ...performed for transferring data to the receive buffer even when the shift in processing of one frame is completed Also no reception completion interrupt is generated When 7 bits is specified for the...

Page 368: ...t INTSTn is generated in synchronization with the completion of the transmission of one frame from the transmit shift register For information about the timing for generating these interrupt requests...

Page 369: ...eption errors explained for the ASISn register Whether a reception error interrupt INTSERn or a reception completion interrupt INTSRn is generated when an error occurs can be specified using the ISRMn...

Page 370: ...e character bit length within one data frame the type of parity and the stop bit length are specified by the asynchronous serial interface mode register n ASIMn n 0 to 2 Also data is transferred with...

Page 371: ...on enabled state a transmit operation is started by writing transmit data to transmit buffer register n TXBn When a transmit operation is started the data in TXBn is transferred to transmit shift regi...

Page 372: ...4V0UM Figure 11 3 Asynchronous Serial Interface Transmission Completion Interrupt Timing Start Stop D0 D1 D2 D6 D7 Parity Parity TXDn output INTSTn output Start D0 D1 D2 D6 D7 TXDn output INTSTn outpu...

Page 373: ...as been written to the TXBn register before writing the next transmit data second byte to the TXBn register If data is written to the TXBn register while the TXBFn bit is 1 the transmit data is not gu...

Page 374: ...s No No No No Yes Yes Transfer executed necessary number of times Write transmit data to TXBn register TXSFn 1 when ASIFn register is read TXSFn 0 when ASIFn register is read TXBFn 0 when ASIFn regist...

Page 375: ...s of the ASIFn register are simultaneously read Therefore use only the TXBFn bit to judge whether data can be written to the TXBn register Remark n 0 to 2 ASIFn register Transmission starting procedur...

Page 376: ...ark n 0 to 2 ASIFn register Transmission ending procedure Internal operation TXBFn TXSFn 6 Transmission of data m 2 is in progress 1 1 7 Generate INTST interrupt Read ASIFn register confirm that the T...

Page 377: ...s generated b Starting a receive operation A receive operation is started by the detection of a start bit The RXDn pin is sampled using the serial clock from the baud rate generator BRGn n 0 to 2 c Re...

Page 378: ...s of the ASISn register are set 1 and a reception error interrupt INTSERn or a reception completion interrupt INTSRn is generated at the same time The ISRMn bit of the ASIMn register specifies whether...

Page 379: ...rs during reception b An error occurs during reception INTSRn output Reception completion interrupt INTSERn output Reception error interrupt INTSRn output Reception completion interrupt INTSERn output...

Page 380: ...is odd b Odd parity i During transmission In contrast to even parity the parity bit is controlled so that the number of bits with the value 1 within the transmit data including the parity bit is odd T...

Page 381: ...the internal circuit see Figure 11 11 See 11 2 6 1 a Basic clock Clock regarding the basic clock Also since the circuit is configured as shown in Figure 11 10 internal processing during a receive oper...

Page 382: ...te generator configuration Figure 11 12 Baud Rate Generator Configuration fXX 2 fXX fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 fXX 1 024 fXX 2 048 Clock fXCLK Selector UARTCAEn 8 bit cou...

Page 383: ...frequency of the basic clock fXCLK is 25 MHz Therefore when the system clock s frequency is 50 MHz bits TPSn3 to TPSn0 cannot be set to 0000B n 0 to 2 If the system clock frequency is 50 MHz set the...

Page 384: ...MDL11 MDL10 FFFFFA17H FFH BRGC2 MDL27 MDL26 MDL25 MDL24 MDL23 MDL22 MDL21 MDL20 FFFFFA27H FFH Bit position Bit name Function Specifies the 8 bit counter s divisor value BR G n7 BR G n6 BR G n5 BR G n4...

Page 385: ...he following formula 100 1 rate baud normal rate baud Desired error with rate baud rate baud Actual Error Cautions 1 Make sure that the baud rate error during transmission does not exceed the allowabl...

Page 386: ...X 25 163 0 15 fXX 26 65 0 16 fXX 24 215 0 07 fXX 23 130 0 16 9 600 fXX 24 163 0 15 fXX 25 65 0 16 fXX 23 215 0 07 fXX 22 130 0 16 19 200 fXX 23 163 0 15 fXX 24 80 0 16 fXX 22 215 0 07 fXX 21 130 0 16...

Page 387: ...t 1 Bit 7 Parity bit Minimum allowable transfer rate Maximum allowable transfer rate Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit Remark n 0...

Page 388: ...Rmin 1 The allowable baud rate error of UARTn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values Table...

Page 389: ...described below n 0 to 2 1 When the supply of clocks to UARTn is stopped for example IDLE or STOP mode operation stops with each register retaining the value it had immediately before the supply of cl...

Page 390: ...or read from the SIOn register 1 Clocked serial interface mode registers 0 to 2 CSIM0 to CSIM2 The CSIMn register is an 8 bit register for specifying the operation of CSIn 2 Clocked serial interface c...

Page 391: ...her or not an interrupt request is generated when the serial clock counter has counted eight serial clocks Figure 11 15 Clocked Serial Interface Block Diagram fXX 215 fXX 214 fXX 212 fXX 210 fXX 28 fX...

Page 392: ...controls the operation of CSIn n 0 to 2 These registers can be read or written in 8 bit or 1 bit units Be sure to set bits 5 3 2 and 1 to 0 If they are set to 1 the operation is not guaranteed Caution...

Page 393: ...gain 6 TRMDn n 0 to 2 Transmission Reception Mode Control Specifies the transmission reception mode 0 Reception only mode 1 Transmission reception mode If TRMDn 0 reception only transfers are performe...

Page 394: ...After reset CSIC0 0 0 0 CKP0 DAP0 CKS02 CKS01 CKS00 FFFFF901H 00H CSIC1 0 0 0 CKP1 DAP1 CKS12 CKS11 CKS10 FFFFF911H 00H CSIC2 0 0 0 CKP2 DAP2 CKS22 CKS21 CKS20 FFFFF921H 00H Bit position Bit name Fun...

Page 395: ...0 fXX 24 Master mode 1 1 1 External clock SCKn Slave mode 2 to 0 CKSn2 to CKSn0 n 0 to 2 Remark fXX Internal system clock a Baud rate Baud Rate bps CKSn2 CKSn1 CKSn0 50 MHz Operation 40 MHz Operation...

Page 396: ...Mn register is cleared 0 These registers are read only in 8 bit units Caution SIOn can be accessed only when the system is in an idle state CSOTn 0 in the CSIMn register 7 6 5 4 3 2 1 0 Address After...

Page 397: ...ept when a reset is input the SIOEn register becomes 00H even when the CSICAEn bit of the CSIMn register is cleared 0 These registers are read only in 8 bit units Caution SIOEn can be accessed only wh...

Page 398: ...ESET input sets the SOTBn register to 00H These registers can be read or written in 8 bit units Caution SOTBn can be accessed only when the system is in an idle state CSOTn 0 in the CSIMn register 7 6...

Page 399: ...d from 0 to 1 serial transfer is not performed 2 Serial clock a When internal clock is selected as the serial clock If reception or transmission is started a serial clock is output from the SCKn pin a...

Page 400: ...Write 55H to SOTBn 55H transmission data CSOTn bit SCKn Reg R W SOTBn SIOn SIn SOn INTCSIn interrupt ABH 56H ADH B5H 6AH D5H AAH 5AH Remark n 0 to 2 b When TRMDn 1 DIRn 0 CKPn 0 and DAPn 1 1 0 1 0 1 0...

Page 401: ...SOTn bit D7 D6 D5 D4 D3 D2 D1 D0 b When CKPn 1 and DAPn 0 INTCSIn interrupt SIn capture SCKn SIOn Reg R W CSOTn bit D7 D6 D5 D4 D3 D2 D1 D0 c When CKPn 0 and DAPn 1 INTCSIn interrupt SIn capture SCKn...

Page 402: ...ixed at low level Remarks 1 When the CKPn bit is overwritten the SCKn pin output changes 2 n 0 to 2 2 SOn pin When CSIn operation is disabled CSICAEn 0 the SOn pin output state is as follows TRMDn DAP...

Page 403: ...O that incorporate a conventional clocked serial interface or a display controller to the V850E MA1 n 2 to 0 When connecting the V850E MA1 to several devices lines for handshake are required Since th...

Page 404: ...2 Sample hold circuit The sample hold circuit samples each of the analog input signals sequentially sent from the input circuit and sends them to the voltage comparator This circuit also holds the sa...

Page 405: ...egister to 0000H 7 Controller The controller selects the analog input generates the sample hold circuit operation timing and controls the conversion trigger according to the mode set by the ADM0 and A...

Page 406: ...ence voltage input pin AVREF that noise may generate an illegal conversion result Software processing will be needed to avoid a negative effect on the system from this illegal conversion result An exa...

Page 407: ...and conversion is executed from the beginning Bit 6 cannot be written to and writing executed is ignored Cautions 1 When the ADCE bit is 1 in the timer trigger mode and external trigger mode the trigg...

Page 408: ...ger mode Timer trigger mode A D trigger mode Timer trigger modeNote 0 0 0 ANI0 ANI0 ANI0 1 0 0 1 ANI1 ANI1 ANI0 ANI1 2 0 1 0 ANI2 ANI2 ANI0 to ANI2 3 0 1 1 ANI3 ANI3 ANI0 to ANI3 4 1 0 0 ANI4 Setting...

Page 409: ...xternal trigger mode is specified by bits 7 and 6 ES1231 ES1230 of the external interrupt mode register INTM3 For details refer to 7 3 9 1 External interrupt mode registers 1 to 4 INTM1 to INTM4 Frequ...

Page 410: ...e ADM0 and ADM1 registers after setting the ADCAE bit of the ADM2 register to 1 it is impossible to write to the ADM0 and ADM1 registers when ADCAE 0 Moreover when the ADCAE bit is set to 0 all regist...

Page 411: ...ister during 16 bit access only the lower 10 bits are valid and the higher 6 bits are always read as 0 15 0 14 0 13 0 12 0 11 0 10 0 9 AD n9 8 AD n8 7 AD n7 6 AD n6 5 AD n5 4 AD n4 3 AD n3 2 AD n2 1 A...

Page 412: ...ion that returns the integer of the value in VIN Analog input voltage AVREF AVREF pin voltage ADCR Value of A D conversion result register ADCRn Figure 12 2 shows the relationship between the analog i...

Page 413: ...of the series resistor string and analog input are compared by the comparator 4 When the comparison of the 10 bits ends the conversion results are stored in the ADCRn register When A D conversion has...

Page 414: ...imer trigger mode and external trigger mode The ANI0 to ANI3 pins are able to specify all of these modes but the ANI4 to ANI7 pins can only specify the A D trigger mode The timer trigger mode consists...

Page 415: ...et by the ADM0 register a Select mode In this mode one analog input specified by the ADM0 register is A D converted The conversion results are stored in the ADCRn register corresponding to the analog...

Page 416: ...7 ANI1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 ANI1 Data 2 ANI1 Data 3 ANI1 Data 4 ANI1 Data 6 ANI1 ADCR1 register INTAD interrupt Conversion start ADM0 register setting ADCE bit set A...

Page 417: ...ing 4 Buffer Mode ANI6 ANI6 input A D conversion Data 1 ANI6 Data 2 ANI6 Data 3 ANI6 Data 4 ANI6 Data 5 ANI6 Data 6 ANI6 Data 7 ANI6 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 ANI6 ADCR0...

Page 418: ...is generated Figure 12 5 Scan Mode Operation Timing 4 Channel Scan ANI0 to ANI3 ANI3 input ANI0 input ANI1 input ANI2 input A D conversion Data 1 ANI0 Data 2 ANI1 Data 3 ANI2 Data 4 ANI3 Data 5 ANI0...

Page 419: ...e conversion results are stored in one ADCRn register The analog input and ADCRn register correspond one to one Each time an A D conversion is executed an A D conversion end interrupt INTAD is generat...

Page 420: ...ster A D conversion can be restarted This mode is suitable for applications in which the average of the A D conversion results is calculated Figure 12 7 Example of 4 Buffer Mode Operation A D Trigger...

Page 421: ...E bit of the ADM0 register A D conversion can be restarted This mode is most appropriate for applications in which multiple analog inputs are constantly monitored Figure 12 8 Example of Scan Mode Oper...

Page 422: ...Tn bit of the TMCCn1 register overflow stop mode to 1 n 0 1 When TMC overflows 0000H is held and counter operation stops Thereafter TMCn does not output the match interrupt signal A D conversion trigg...

Page 423: ...onverted once using the trigger of the match interrupt signal INTM000 and the results are stored in one ADCRn register An A D conversion end interrupt INTAD is generated for each A D conversion and A...

Page 424: ...tarted is generated the ADCS bit is set 1 and A D conversion is started n 0 1 When set to the loop mode unless the ADCE bit of the ADM0 register is set to 0 A D conversion is repeated each time a matc...

Page 425: ...egister INTM000 interrupt ANIn ADCR0 INTM000 interrupt ANIn ADCR1 INTM000 interrupt ANIn ADCR2 INTM000 interrupt ANIn ADCR3 If the one shot mode is set and the TMCCE0 bit of the TMCC00 register is set...

Page 426: ...ster is set to 0 A D conversion is repeated each time a match interrupt is generated The match interrupts INTM000 INTM001 INTM010 INTM011 can be generated in any order and the conversion results are s...

Page 427: ...the specified analog inputs has ended the A D conversion end interrupt INTAD is generated and A D conversion is stopped n 0 to 7 There are two scan modes 1 trigger mode and 4 trigger mode according to...

Page 428: ...1 is A D converted 13 The conversion result is stored in ADCR3 7 The conversion result is stored in ADCR1 14 The INTAD interrupt is generated Caution INTM0nn cannot be used as a trigger for the analog...

Page 429: ...onversion Result Register INTM000 interrupt ANI0 ADCR0 INTM001 interrupt ANI1 ADCR1 INTM010 interrupt ANI2 ADCR2 INTM011 interrupt ANI3 ADCR3 ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 A D trigger mode ANI7 ADC...

Page 430: ...erted 6 ANI3 is A D converted 13 The conversion result is stored in ADCR2 7 The conversion result is stored in ADCR3 14 The INTAD interrupt is generated Caution INTM0nn cannot be used as a trigger for...

Page 431: ...select modes 1 buffer mode and 4 buffer mode according to the storing method of the A D conversion results n 0 to 3 1 1 buffer mode external trigger select 1 buffer In this mode one analog input is A...

Page 432: ...ger is input from the ADTRG pin This mode is suitable for applications in which calculate the average of A D conversion result is calculated Figure 12 16 Example of 4 Buffer Mode Operation External Tr...

Page 433: ...analog input are set by the ADM0 register so that they are scanned after the conversion of the lower 4 channels is ended the mode is shifted to the A D trigger mode and the remaining A D conversions...

Page 434: ...ANI1 is A D converted 13 The conversion result is stored in ADCR3 7 The conversion result is stored in ADCR1 14 The INTAD interrupt is generated Caution ADTRG cannot be used as a trigger for the anal...

Page 435: ...register and the number of trigger input are not counted Note therefore that the saving of the result to the ADCRn register upon the generation of an interrupt is an abnormality n 0 to 7 3 When interv...

Page 436: ...start trigger and starts the conversion operation When this happens the compare register s match interrupt also functions as a compare register match interrupt for the CPU In order to prevent match in...

Page 437: ...llows independently of the resolution 1 FSR Maximum value of convertible analog input voltage Minimum value of convertible analog input voltage 100 AVREF 0 100 AVREF 100 Where the resolution is 10 bit...

Page 438: ...total error zero scale error full scale error integral linearity error and differential linearity error in the characteristic table Figure 12 19 Quantization Error Quantization error 1 1 0 0 0 AVREF A...

Page 439: ...ror AVREF Analog input LSB Digital output lower 3 bits 111 AVREF 3 0 AVREF 2 AVREF 1 100 011 010 000 Full scale errors 6 Differential linearity error Ideally the width to output a specific code is 1 L...

Page 440: ...re the zero scale error and full scale error are 0 Figure 12 23 Integral Linearity Error 1 1 0 0 0 AVREF Analog input Digital output Ideal line Integral linearity errors 8 Conversion time This is the...

Page 441: ...g 8 9 10 12 bits Remark n 0 1 13 2 Block Diagram Counter TMPn Edge latch Comparator Compare register CMPn Level latch PWM buffer register PWMBn Level latch 0 to 7 0 to 8 0 to 9 0 to 11 12 12 12 PWM co...

Page 442: ...is used to control the PWMn s operations n 0 1 The PWMCn register can be read written in 8 bit or 1 bit units Caution When PWMn is used be sure to set external pins related to PWMn to control mode Fol...

Page 443: ...egister CMPn PRMn1 PRMn0 Bit length for TMPn and CMPn 0 0 8 bits 0 1 9 bits 1 0 10 bits 1 1 12 bits 5 4 PRMn1 PRMn0 n 0 1 PWM Prescaler Clock Mode This bit is used to select the PWMn s operating clock...

Page 444: ...B3 2 PWM B2 1 PWM B1 0 PWM B0 PWMB1 Address FFFFFC02H After reset 0000H Address FFFFFC12H After reset 0000H 13 4 Operation 13 4 1 Basic operations When a PWMn pulse is output the required data is firs...

Page 445: ...rator match signal Reload PWMn Output Set Reset Set Full count FEH count Remark n 0 1 Figure 13 2 Timing for Write Operation to PWMBn Register Counter Overflow signal PWMEn bit PWMBn register M CMPn r...

Page 446: ...or match signal PWMn Output FEH FFH 00H 01H FEH 00H 01H 02H FEH FFH 00H 01H 02H FFH Counter 00H Not set to active level L Remark n 0 1 Figure 13 4 Timing When PWMBn Register Is Set to FFH Overflow sig...

Page 447: ...9 bits 10 bits 12 bits fXX 212 fXX 213 fXX 214 fXX 216 fXX 32 8 bits 9 bits 10 bits 12 bits fXX 213 fXX 214 fXX 215 fXX 217 fXX 64 8 bits 9 bits 10 bits 12 bits fXX 214 fXX 215 fXX 216 fXX 218 Remark...

Page 448: ...al U14359EJ4V0UM 448 CHAPTER 14 PORT FUNCTIONS 14 1 Features Input only ports 9 Input output ports 106 Function alternately as other peripheral I O pins It is possible to specify input and output in 1...

Page 449: ...through 5 and AL AH DL CS CT CM CD and BD The port configuration is shown below Port 0 P00 to P07 Port 1 P10 to P13 Port 2 P21 to P27 P20 Port 3 P30 to P37 Port 4 P40 to P45 Port 5 P50 to P52 Port 7...

Page 450: ...eal time pulse unit RPU I O External interrupt input A B Port 7 P70 to P77 8 bit input A D converter input C Port AL PAL0 to PAL15 16 bit I O External address bus A0 to A15 J Port AH PAH0 to PAH9 10 b...

Page 451: ...TI010 P11 input mode P12 INTP011 P12 input mode Port 1 P13 TO01 P13 input mode PMC1 P20 NMI NMI P21 INTP020 TI020 P21 input mode P22 INTP021 P22 input mode P23 TO02 P23 input mode PMC2 P24 TC0 INTP11...

Page 452: ...DQM PCT1 UCAS UWR UDQM PCT1 input mode UCAS UWR UDQM PCT4 RD PCT4 input mode RD PCT5 WE PCT5 input mode WE PCT6 OE PCT6 input mode OE Port CT PCT7 BCYST PCT7 input mode BCYST PMCCT PCS0 CS0 PCS0 input...

Page 453: ...ual U14359EJ4V0UM 453 3 Block diagram of port Figure 14 1 Block Diagram of Type A Internal bus WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Output signal in control mode Selector Selector Selector Pmn Addres...

Page 454: ...WRPM WRPORT RDIN PMCmn PMmn Pmn Selector Selector Pmn Address Noise elimination Edge detection Input signal in control mode Internal bus Remark m Port number n Bit number Figure 14 3 Block Diagram of...

Page 455: ...NCTIONS User s Manual U14359EJ4V0UM 455 Figure 14 4 Block Diagram of Type D WRPMC MODE0 to MODE2 WRPORT RDIN PMCCMn WRPM PMCMn PCMn PCMn Address Input signal in control mode Internal bus Selector Sele...

Page 456: ...5 Block Diagram of Type E WRPM WRPORT RDIN PMCM5 PCM5 PCM5 Address Input signal in control mode Internal bus Selector Selector WRPMC MODE0 to MODE2 PMCCM5 Figure 14 6 Block Diagram of Type F RDIN P20...

Page 457: ...S User s Manual U14359EJ4V0UM 457 Figure 14 7 Block Diagram of Type G WRPMC WRPM RDIN PMC4n PM4n WRPORT P4n P4n Address Output signal in control mode Internal bus Selector Selector Selector Selector W...

Page 458: ...al U14359EJ4V0UM 458 Figure 14 8 Block Diagram of Type H WRPFC WRPMC WRPM WRPORT RDIN PFCmn PMCmn PMmn Pmn Pmn Address Input signal in control mode Internal bus Selector Selector Selector Edge detecti...

Page 459: ...9EJ4V0UM 459 Figure 14 9 Block Diagram of Type I WRPFC WRPMC WRPM WRPORT RDIN PFC32 PMC32 PM32 P32 P32 SCK2 output enable signal Address Input signal in control mode Output signal in control mode Inte...

Page 460: ...Manual U14359EJ4V0UM 460 Figure 14 10 Block Diagram of Type J WRPM WRPORT RDIN PMmn WRPMC PMCmn Pmn Pmn MODE0 to MODE2 Address Output signal in control mode Internal bus Selector Selector Selector Re...

Page 461: ...4359EJ4V0UM 461 Figure 14 11 Block Diagram of Type K WRPFC MODE0 to MODE2 WRPMC WRPM WRPORT RDIN PFCmn PMCmn PMmn Pmn Pmn Address Output signal in control mode Internal bus Selector Selector Selector...

Page 462: ...anual U14359EJ4V0UM 462 Figure 14 12 Block Diagram of Type L WRPMC WRPM RDIN PMC3n PM3n WRPORT P3n P3n Address Output signal in control mode Internal bus Selector Selector Selector WRPFC PFC3n Input s...

Page 463: ...463 Figure 14 13 Block Diagram of Type M WRPMC WRPM WRPORT RDIN PMC4n PM4n P4n P4n Address Input signal in control mode Output signal in control mode SCKx output enable signal Internal bus Selector S...

Page 464: ...9EJ4V0UM 464 Figure 14 14 Block Diagram of Type N WRPMC WRPM RDIN PMC2n PM2n WRPORT P2n P2n Address Output signal in control mode Internal bus Selector Selector Selector WRPFC PFC2n Input signal in co...

Page 465: ...M 465 Figure 14 15 Block Diagram of Type O WRPM WRPORT RDIN PMDLn WRPMC PMCDLn PDLn PDLn Address Output signal in control mode Input signal in control mode I O control Internal bus Selector Selector S...

Page 466: ...TI000 External interrupt request input Real time pulse unit RPU input P02 INTP001 External interrupt request input B P03 TO00 Real time pulse unit RPU output A Port 0 P04 to P07 DMARQ0 INTP100 to DMAR...

Page 467: ...I O port mode 1 TO00 output mode 2 PMC02 Port Mode Control Specifies operation mode of P02 pin 0 I O port mode 1 External interrupt request INTP001 input mode 1 PMC01 Port Mode Control Specifies opera...

Page 468: ...Caution When the port mode is specified by the port 0 mode control register PMC0 the PFC0 setting becomes invalid 7 6 5 4 3 2 1 0 Address After reset PFC0 PFC07 PFC06 PFC05 PFC04 0 0 0 0 FFFFF460H 00H...

Page 469: ...rk Block Type P10 PWM1 PWM output A P11 TI010 INTP010 External interrupt request input Real time pulse unit RPU input P12 INTP011 External interrupt request input B Port 1 P13 TO01 Real time pulse uni...

Page 470: ...l interrupt request INTP011 input mode 1 PMC11 Port Mode Control Specifies operation mode of P11 pin 0 I O port mode 1 External interrupt request INTP010 input mode TI010 input mode There is no regist...

Page 471: ...to 1 P2n n 7 to 1 Port 2 I O port In addition to their function as port pins the port 2 pins can also operate as the real time pulse unit RPU I O external interrupt request inputs and the DMA end ter...

Page 472: ...2 mode control register PMC2 and the port 2 function control register PFC2 a Port 2 mode register PM2 This register can be read written in 8 bit or 1 bit units 7 6 5 4 3 2 1 0 Address After reset PM2...

Page 473: ...Specifies operation mode of P23 pin 0 I O port mode 1 TO02 output mode 2 PMC22 Port Mode Control Specifies operation mode of P22 pin 0 I O port mode 1 External interrupt request INTP021 input mode 1...

Page 474: ...gnored Caution When the port mode is specified by the port 2 mode control register PMC2 the PFC2 setting becomes invalid 7 6 5 4 3 2 1 0 Address After reset PFC2 PFC27 PFC26 PFC25 PFC24 0 0 0 0 FFFFF4...

Page 475: ...I O External interrupt request inputs I P33 TXD2 INTP133 L P34 RXD2 INTP120 Serial interface UART2 I O External interrupt request inputs H P35 INTP121 P36 INTP122 External interrupt request inputs Por...

Page 476: ...an external trigger mode using the ADM1 register 6 PMC36 Port Mode Control Specifies operation mode of P36 pin 0 I O port mode 1 External interrupt request INTP122 input mode 5 PMC35 Port Mode Control...

Page 477: ...ies operation mode of P34 pin in control mode 0 RXD2 input mode 1 External interrupt request INTP120 input mode 3 PFC33 Port Function Control Specifies operation mode of P33 pin in control mode 0 TXD2...

Page 478: ...P40 TXD0 SO0 G P41 RXD0 SI0 H P42 SCK0 Serial interface UART0 CSI0 I O M P43 TXD1 SO1 G P44 RXD1 SI1 H Port 4 P45 SCK1 Serial interface UART1 CSI1 I O M 2 I O mode control mode setting The port 4 I O...

Page 479: ...5 pin 0 I O port mode 1 SCK1 I O mode 4 PMC44 Port Mode Control Specifies operation mode of P44 pin 0 I O port mode 1 RXD1 SI1 input mode 3 PMC43 Port Mode Control Specifies operation mode of P43 pin...

Page 480: ...Address After reset PFC4 0 0 0 PFC44 PFC43 0 PFC41 PFC40 FFFFF468H 00H Bit position Bit name Function 4 PFC44 Port Function Control Specifies operation mode of P44 pin in control mode 0 SI1 input mode...

Page 481: ...on Remark Block Type P50 INTP030 TI030 External interrupt request input Real time pulse unit RPU input P51 INTP031 External interrupt request input B Port 5 P52 TO03 Real time pulse unit RPU output A...

Page 482: ...mode of P51 pin 0 I O port mode 1 External input request INTP031 input mode 0 PMC50 Port Mode Control Specifies operation mode of P50 pin 0 I O port mode 1 External interrupt request INTP030 input mod...

Page 483: ...ion as port pins the port 7 pins can also operate as the analog inputs to the A D converter in the control mode 1 Operation in control mode Port Alternate Function Remark Block Type Port 7 P77 to P70...

Page 484: ...ontrol mode Port Alternate Function Remark Block Type Port AL PAL15 to PAL0 A15 to A0 Address bus when memory expanded J 2 I O mode control mode setting The port AL I O mode setting is performed by th...

Page 485: ...t port mode registers can be read written in 8 bit or 1 bit units 15 14 13 12 11 10 9 8 Address After resetNote PMCAL PMCAL15 PMCAL14 PMCAL13 PMCAL12 PMCAL11 PMCAL10 PMCAL9 PMCAL8 FFFFF041H FFFFH 0000...

Page 486: ...0 of port AH bits 7 to 2 of port AHH are undefined 15 14 13 12 11 10 9 8 Address After reset PAH PAH9 PAH8 FFFFF003H Undefined 7 6 5 4 3 2 1 0 Address PAH7 PAH6 PAH5 PAH4 PAH3 PAH2 PAH1 PAH0 FFFFF002H...

Page 487: ...sition Bit name Function 9 to 0 PMAHn n 9 to 0 Port Mode Specifies input output mode for PAHn pin 0 Output mode output buffer on 1 Input mode output buffer off b Port AH mode control register PMCAH Th...

Page 488: ...mode Port Alternate Function Pin Name Remark Block Type Port DL PDL15 to PDL0 D15 to D0 Data bus when memory expanded O 2 I O mode control mode setting The port DL I O mode setting is performed by the...

Page 489: ...written in 8 bit or 1 bit units 15 14 13 12 11 10 9 8 Address After resetNote PMCDL PMCDL15 PMCDL14 PMCDL13 PMCDL12 PMCDL11 PMCDL10 PMCDL9 PMCDL8 FFFFF045H FFFFH 0000H 7 6 5 4 3 2 1 0 Address PMCDL7 P...

Page 490: ...uts when memory is externally expanded the row address strobe signal outputs to DRAM and the read write strobe signal output to an external I O 1 Operation in control mode Port Alternate Function Pin...

Page 491: ...control register PMCCS and the port CS function control register PFCCS a Port CS mode register PMCS This register can be read written in 8 bit or 1 bit units 7 6 5 4 3 2 1 0 Address After reset PMCS...

Page 492: ...rt Mode Control Specifies operation mode of PCS5 pin 0 I O port mode 1 CS5 output mode IORD output mode 4 PMCCS4 Port Mode Control Specifies operation mode of PCS4 pin 0 I O port mode 1 CS4 RAS4 outpu...

Page 493: ...ing becomes invalid 7 6 5 4 3 2 1 0 Address After reset PFCCS 0 0 PFCCS5 0 0 PFCCS2 0 0 FFFFF049H 00H Bit position Bit name Function 5 PFCCS5 Port Function Control Specifies operation mode of PCS5 pin...

Page 494: ...disable write mask signal PCT1 UCAS UWR UDQM Column address signal output write strobe signal output output disable write mask signal PCT4 RD Read strobe signal output PCT5 WE Write enable signal out...

Page 495: ...T6 Port Mode Control Specifies operation mode of PCT6 pin 0 I O port mode 1 OE output mode 5 PMCCT5 Port Mode Control Specifies operation mode of PCT5 pin 0 I O port mode 1 WE output mode 4 PMCCT4 Por...

Page 496: ...on signal input D PCM1 CLKOUT BUSCLK Internal system clock output bus clock output K PCM2 HLDAK Bus hold acknowledge signal output J PCM3 HLDRQ Bus hold request signal input D PCM4 REFRQ Refresh reque...

Page 497: ...PMCCM4 PMCCM3 PMCCM2 PMCCM1 PMCCM0 FFFFF04CH 00H 3FH Note In ROMless modes 0 and 1 and single chip mode 1 3FH In single chip mode 0 00H Bit position Bit name Function 5 PMCCM5 Port Mode Control Speci...

Page 498: ...bit of the BCP register is set to 1 with the CLKOUT output mode selected the external bus operates at half the frequency of the internal system clock frequency but the CLKOUT pin outputs the internal...

Page 499: ...in Name Remark Block Type PCD0 SDCKE Clock enable signal output PCD1 SDCLK Synchronous clock output J PCD2 LBE SDCAS Byte enable signal output column address strobe signal output Port CD PCD3 UBE SDRA...

Page 500: ...BE output mode When using SDRAM be sure to set the SDRAS output mode and SDCAS output mode using the PFCCD register 7 6 5 4 3 2 1 0 Address After resetNote PMCCD 0 0 0 0 PMCCD3 PMCCD2 PMCCD1 PMCCD0 FF...

Page 501: ...port mode is specified by the port CD mode control register PMCCD the PFCCD setting becomes invalid 7 6 5 4 3 2 1 0 Address After reset PFCCD 0 0 0 0 PFCCD3 PFCCD2 0 0 FFFFF04FH 00H Bit position Bit n...

Page 502: ...mode Port Alternate Function Pin Name Remark Block Type Port BD PBD0 to PBD3 DMAAK0 to DMAAK3 DMA acknowledge signal output J 2 I O mode control mode setting The port BD I O mode setting is performed...

Page 503: ...This register can be read written in 8 bit or 1 bit units 7 6 5 4 3 2 1 0 Address After reset PMCBD 0 0 0 0 PMCBD3 PMCBD2 PMCBD1 PMCBD0 FFFFF052H 00H Bit position Bit name Function 3 to 0 PMCBDn n 3 t...

Page 504: ...L AH DL CS CT CM CD and BD If no resistor is connected external memory may be destroyed when these pins enter the high impedance state For the same reason the output pins of the internal peripheral I...

Page 505: ...set signal continues in the active state for at least 4 system clock cycles after reset clear timing by the RESET signal 2 Reset when turning on the power In a reset operation when the power is turned...

Page 506: ...xception debug trap DBPC DBPSW Undefined CPU System registers CALLT base pointer CTBP Undefined Internal RAM Undefined Ports P0 to P5 P7 PAL PAH PDL PCS PCT PCM PCD PBD Undefined Mode registers PM0 to...

Page 507: ...A D converter mode registers 0 and 2 ADM0 and ADM2 00H A D converter mode register 1 ADM1 07H A D conversion result register n 10 bits n 0 to 7 0000H A D converter A D conversion result register nH 8...

Page 508: ...Bus cycle control register BCC FFFFH Bus cycle period control register BCP 00H Bus cycle type configuration register n BCTn n 0 1 8888H Endian configuration register BEC 0000H Bus size configuration...

Page 509: ...an be changed after the V850E MA1 is solder mounted on the target system Small scale production of various models is made easier by differentiating software Data adjustment in starting mass production...

Page 510: ...are not indicated should be connected according to the recommended connections of unused pins refer to 2 4 Pin I O Circuits and Recommended Connection of Unused Pins When connecting to VDD via a resi...

Page 511: ...SCK0 68 P42 SCK0 68 CLK Output Clock to V850E MA1 X1 63 X1 63 CKSEL Input CG mode setting CKSEL 60 CKSEL 60 RESET Output Reset signal RESET 59 RESET 59 VPP Output Write voltage VPP MODE2 18 VPP MODE2...

Page 512: ...5 N5 N10 Remarks 1 Pins whose connections are not indicated should be connected according to the recommended connections of unused pins refer to 2 4 Pin I O Circuits and Recommended Connection of Unus...

Page 513: ...N11 P42 SCK0 N11 CLK Output Clock to V850E MA1 X1 P10 X1 P10 CKSEL Input CG mode setting CKSEL M9 CKSEL M9 RESET Output Reset signal RESET L9 RESET L9 VPP Output Write voltage VPP MODE2 G1 VPP MODE2...

Page 514: ...icated flash programmer and the V850E MA1 to perform writing erasing etc A dedicated program adapter FA Series is required for off board writing 16 4 Communication Mode 1 CSI0 Transfer rate Up to 2 MH...

Page 515: ...V is input to the MODE2 VPP pin In the flash memory programming mode a 7 8 V writing voltage is supplied to the MODE2 VPP pin The following shows an example of the connection of the MODE2 VPP pin V85...

Page 516: ...t connected to another device input the signal output to the other device may cause the device to malfunction To avoid this isolate the connection to the other device or set so that the input signal t...

Page 517: ...ot change the signal input to the NMI pin in flash memory programming mode If it is changed in flash memory programming mode programming may not be performed correctly 16 5 5 MODE0 to MODE2 pins If MO...

Page 518: ...9EJ4V0UM 16 6 Programming Method 16 6 1 Flash memory control The following shows the procedure for manipulating the flash memory Start Switch to flash memory programming mode Supply RESET pulse Select...

Page 519: ...nput MODE2 VPP 7 8 V n 1 Flash memory programming mode MODE0 MODE1 1 0 1 1 7 8 V MODE2 VPP 3 V 0 V RESET 2 16 6 3 Selection of communication mode In the V850E MA1 the communication mode is selected by...

Page 520: ...Checks the erase state of the entire memory Blank check Block blank check command Checks the erase state of the specified memory block High speed write command Writes data by the specification of the...

Page 521: ...ram placed in the block 0 space 000000H to 1FFFFFH and areas other than internal ROM area To place the program in the block 0 space and internal ROM area copy the program to areas other than 000000H t...

Page 522: ...in which an over erase occurred Acquire information Flash memory information read Reads out information about flash memory 16 7 3 Outline of self programming interface To execute self programming usi...

Page 523: ...To write or erase the flash memory a high voltage must be applied to the VPP pin To execute self programming a circuit that can generate a write voltage VPP and that can be controlled by software is n...

Page 524: ...sh memory starts until manipulation is complete Cautions 1 Apply 0 V to the VPP pin when reset is released 2 Implement self programming in single chip mode 0 or 1 3 Apply the voltage to the VPP pin in...

Page 525: ...mer while the flash memory is being manipulated Because the internal timer is initialized after the flash memory has been used initialize the timer with the application program to use the timer again...

Page 526: ...nction numbers are used as parameters when the device internal processing is called Table 16 6 Self Programming Function Number Function No Function Name 0 Acquiring flash information 1 Erasing area 2...

Page 527: ...fy start address Number of bytes to be verified 0 Normal completion Other than 0 Error Erase verify 10 None acts on erase manipulation area immediately before 0 Normal completion Other than 0 Error Su...

Page 528: ...If write back time is 1 ms 1 1 000 100 10 integer operation ep 0x10 2 bytes Input Timer set value for creating internal operation unit time unsigned 2 bytes Write a set value that makes the value of...

Page 529: ...ation For the flash information acquisition function function No 0 the option number r7 to be specified and the contents of the return value r10 are as follows To acquire all flash information call th...

Page 530: ...number The area numbers and memory map of the PD70F3107A are shown below Figure 16 7 Area Configuration Area 1 128 KB Area 0 128 KB 0 x 3 F F F F End address of area 1 0 x 0 0 0 0 0 Start address of a...

Page 531: ...able Enables disables writing deleting on chip flash memory When this bit is 1 writing deleting on chip flash memory is disabled even if a high voltage is applied to the VPP pin 0 Enables writing dele...

Page 532: ...C r0 5 NOP 6 NOP 7 NOP 8 NOP 9 NOP 10 LDSR rY 5 Remark rX Value written to the PSW rY Value returned to the PSW No special sequence is required for reading a specific register Cautions 1 If an interru...

Page 533: ...lash memory FLSPM bit 0 to select normal operation mode 7 Wait for the internal manipulation setup time see 16 7 13 5 Internal manipulation setup parameter 1 Parameter r6 First argument sets a self pr...

Page 534: ...ipulation setup parameter EntryProgram add 4 sp Prepare st w lp 0 sp Save return address movea lo 0x00a0 r0 r10 ldsr r10 5 PSW NP ID mov lo 0x0002 r10 st b r10 PHCMD r0 PHCMD 2 st b r10 FLPMC r0 VPPDI...

Page 535: ...sh memory In the program example in 4 above the elapse of this wait time is ensured by setting ISETUP to 130 50 MHz operation The total number of execution clocks in this example is 39 clocks divh ins...

Page 536: ...et RAM parameter Mask interrupts Pre write Erase area Erase byte verify Erase verify Area write back Erase verify Clear number of times write back is repeated Erase byte verify Write error Undererase...

Page 537: ...data in word units is illustrated below The processing of each function number must be executed in accordance with the specified calling procedure Figure 16 9 Successive Writing Flow Function No 16 Y...

Page 538: ...processing of each function number must be executed in accordance with the specified calling procedure Figure 16 10 Internal Verify Flow Function No 21 Yes No Internal verify Mask interrupts Set VPP...

Page 539: ...nformation is illustrated below The processing of each function number must be executed in accordance with the specified calling procedure Figure 16 11 Acquiring Flash Information Flow Function No 0 A...

Page 540: ...ng module is located in area 0 and the data in area 1 is rewritten or erased The rewriting module is a user program to rewrite the flash memory The other areas can be also rewritten by using the flash...

Page 541: ...the self programming library is outlined below Figure 16 13 Outline of Self Programming Library Configuration Application program Entry program RAM parameter Device internal processing Flash memory Se...

Page 542: ...NOP 7 NOP 8 NOP 9 LDSR rY 5 10 TST1 3 FLPMC r0 BNZ Start address of self programming routine BR Routine when writing is not performed Remark rX Value written to the PSW rY Value returned to the PSW C...

Page 543: ...ADC 411 ADCR7H A D conversion result register 7H 8 bits ADC 411 ADIC Interrupt control register INTC 281 ADM0 A D converter mode register 0 ADC 407 ADM1 A D converter mode register 1 ADC 409 ADM2 A D...

Page 544: ...e register D1 RPU 351 CMD2 Compare register D2 RPU 351 CMD3 Compare register D3 RPU 351 CMICD0 Interrupt control register INTC 280 CMICD1 Interrupt control register INTC 280 CMICD2 Interrupt control r...

Page 545: ...n address register 3L DMAC 211 DDIS DMA disable status register DMAC 216 DMAIC0 Interrupt control register INTC 280 DMAIC1 Interrupt control register INTC 280 DMAIC2 Interrupt control register INTC 28...

Page 546: ...control register INTC 280 P00IC1 Interrupt control register INTC 280 P01IC0 Interrupt control register INTC 280 P01IC1 Interrupt control register INTC 280 P02IC0 Interrupt control register INTC 280 P0...

Page 547: ...FCCD Port CD function control register Port 501 PFCCM Port CM function control register Port 498 PFCCS Port CS function control register Port 493 PHCMD Peripheral command register CPU 302 PHS Peripher...

Page 548: ...ister CPU 309 PSC Power save control register CPU 310 PSMR Power save mode register CPU 309 PWMB0 PWM buffer register 0 PWM 444 PWMB1 PWM buffer register 1 PWM 444 PWMC0 PWM control register 0 PWM 442...

Page 549: ...O shift register 1 CSI1 397 SIOE2 Receive only serial I O shift register 2 CSI2 397 SOTB0 Clocked serial interface transmit buffer register 0 CSI0 398 SOTB1 Clocked serial interface transmit buffer r...

Page 550: ...rol register D1 RPU 353 TMCD2 Timer mode control register D2 RPU 353 TMCD3 Timer mode control register D3 RPU 353 TMD0 Timer D0 RPU 350 TMD1 Timer D1 RPU 350 TMD2 Timer D2 RPU 350 TMD3 Timer D3 RPU 35...

Page 551: ...5 bit data that specifies the trap vector 00H to 1FH cccc 4 bit data that shows the conditions code sp Stack pointer r3 ep Element pointer r30 listX X item register list 2 Register symbols used to des...

Page 552: ...n 80000000H let it be 80000000H result Reflects the results in a flag Byte Byte 8 bits Half word Halfword 16 bits Word Word 32 bits Addition Subtraction ll Bit concatenation Multiplication Division R...

Page 553: ...OV 0 No overflow C L 0 0 0 1 CY 1 Carry Lower Less than NC NL 1 0 0 1 CY 0 No carry Not lower Greater than or equal Z E 0 0 1 0 Z 1 Zero Equal NZ NE 1 0 1 0 Z 0 Not zero Not equal NH 0 0 1 1 CY or Z...

Page 554: ...0 0 00 0 wwwww01101000000 GR reg3 GR reg2 7 0 ll GR reg2 15 8 ll GR reg2 23 16 ll GR reg2 31 24 1 1 1 0 CALLT imm6 0 0 0 0 0 0 1 0 0 0 i i i i i i CTPC PC 2 return PC CTPSW PSW adr CTBP zero extend im...

Page 555: ...000010RRRRR GR reg2 GR reg2 GR reg1 Note 6 35 35 35 DIVH reg1 reg2 reg3 rrrrr111111RRRRR wwwww01010000000 GR reg2 GR reg2 GR reg1 Note 6 GR reg3 GR reg2 GR reg1 35 35 35 DIVHU reg1 reg2 reg3 rrrrr1111...

Page 556: ...rr110010RRRRR i i i i i i i i i i i i i i i i GR reg2 GR reg1 imm16 ll 016 1 1 1 reg1 reg2 reg3 rrrrr111111RRRRR wwwww01000100000 GR reg3 ll GR reg2 GR reg2 GR reg1 1 2 Note14 2 MUL imm9 reg2 reg3 r r...

Page 557: ...PSW EIPSW else if PSW NP 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW 4 4 4 R R R R R reg1 reg2 rrrrr111111RRRRR 0000000010100000 GR reg2 GR reg2 arithmetically shift right by GR reg1 1 1 1 0 SAR i...

Page 558: ...zero extend disp4 GR reg2 zero extend Load memory adr Byte 1 1 Note9 SLD H disp8 ep reg2 r rr r r 10 0 0 dd d d dd d Note 19 adr ep zero extend disp8 GR reg2 sign extend Load memory adr Halfword 1 1...

Page 559: ...te3 3 Note3 TST1 reg2 reg1 rrrrr111111RRRRR 0000000011100110 adr GR reg1 Z flag Not Load memory bit adr reg2 3 Note3 3 Note3 3 Note3 XOR reg1 reg2 rrrrr001001RRRRR GR reg2 GR reg2 XOR GR reg1 1 1 1 0...

Page 560: ...4 bits of imm9 14 In the case of reg2 reg3 the lower 32 bits of the results are not written in the register or reg3 r0 the higher 32 bits of the results are not written in the register shortened by 1...

Page 561: ...Basic configuration of timer D 349 Baud rate generator control registers 0 to 2 384 BCC 126 BCP 122 BCT0 BCT1 102 BCYST 56 BEC 105 Block transfer mode 227 Boundary operation conditions 140 BRG0 to BR...

Page 562: ...address registers 0H to 3H 210 DMA destination address registers 0L to 3L 211 DMA disable status register 216 DMA restart register 216 DMA source address registers 0H to 3H 208 DMA source address regi...

Page 563: ...lag 283 Maskable interrupts 272 Maximum response time for DMA transfer request 261 Memory block function 97 Memory map 75 MODE0 to MODE2 60 Multiple interrupt processing control 295 N Next address set...

Page 564: ...configuration 31 Pin I O circuits 64 Pin I O circuits and recommended connection of unused pins 62 Pin status 46 PLL lockup 306 PLL mode 302 PM0 466 PM1 469 PM2 472 PM3 475 PM4 478 PM5 481 PMAH 487 PM...

Page 565: ...rescaler unit 299 Priorities of maskable interrupts 275 Program register set 67 Program space 140 Programmable wait function 119 PRS 299 PSC 310 PSMR 309 PWM buffer registers 0 1 444 PWM control regis...

Page 566: ...nal count output upon DMA transfer end 259 TI000 47 TI010 48 TI020 49 TI030 52 Time base counter 322 Timer C 323 Timer C operation 334 Timer D 349 Timer D operation 355 Timer mode control registers C0...

Page 567: ...886 2 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 211 6503 2...

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