CHAPTER 9 CLOCK GENERATION FUNCTION
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User’s Manual U14359EJ4V0UM
9.5.3 HALT mode
(1) Setting and operation status
In HALT mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the operation
clock of the CPU is stopped. Since the supply of clocks to on-chip peripheral I/O units other than the CPU
continues, operation continues. The power consumption of the overall system can be reduced by setting the
system to HALT mode while the CPU is idle.
The system is switched to HALT mode by the HALT instruction.
Although program execution stops in HALT mode, the contents of all registers, internal RAM, and ports are
maintained in the state they were in immediately before HALT mode began. Also, operation continues for all
on-chip peripheral I/O units (other than ports) that do not depend on CPU instruction processing. Table 9-2
shows the status of each hardware unit in HALT mode.
Caution
If the HALT instruction is executed while an interrupt is being held pending, the HALT mode
is set once but it is immediately released by the pending interrupt request.
Table 9-2. Operation Status in HALT Mode
Function
Operation Status
Clock generator
Operating
Internal system clock
Operating
CPU
Stopped
Ports
Maintained
On-chip peripheral I/O (excluding ports)
Operating
Internal data
All internal data such as CPU registers, statuses, data, and
the contents of internal RAM are maintained in the state
they were in immediately before HALT mode began.
D0 to D15
A0 to A25
RD, WE, OE, BCYST
UWR, LWR, IORD, IOWR
LDQM, UDQM
CS0 to CS7
LCAS, UCAS
RAS1, RAS3, RAS4, RAS6
SDRAS
SDCAS
REFRQ
HLDAK
HLDRQ
WAIT
SELFREF
SDCKE
Operating
SDCLK
CLKOUT
Clock output
