CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
(3) SDRAM access timing control
The SDRAM access timing can be controlled by SDRAM configuration register n (SCRn) (n = 1, 3, 4, 6). For
details, see
5.4.4 SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6)
.
Caution
Wait control by the WAIT pin is not available during SDRAM access.
(a) Number of waits from bank active command to read/write command
The number of wait states from bank active command issue to read/write command issue can be set by
setting the BCW1n and BCW0n bits of the SCRn register.
BCW1n, BCW0n = 01B:
1 wait
BCW1n, BCW0n = 10B:
2 waits
BCW1n, BCW0n = 11B:
3 waits
(b) Number of waits from precharge command to bank active command
The number of wait states from precharge command issue to bank active command issue can be set by
setting the BCW1n and BCW0n bits of the SCRn register.
BCW1n, BCW0n = 01B:
1 wait
BCW1n, BCW0n = 10B:
2 waits
BCW1n, BCW0n = 11B:
3 waits
(c) CAS latency setting when read
The CAS latency during a read operation can be set by setting the LTM2n to LTM0n bits of the SCRn
register.
LTM2n to LTM0n = 010B:
Latency = 2
LTM2n to LTM0n = 011B:
Latency = 3
(d) Number of waits from refresh command to next command
The number of wait states from refresh command issue to next command issue can be set by setting the
BCW1n and BCW0n bits of the SCRn register. The number of wait states becomes four times the value
set by BCW1n and BCW0n.
BCW1n, BCW0n = 01B:
4 waits
BCW1n, BCW0n = 10B:
8 waits
BCW1n, BCW0n = 11B:
12 waits
