CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
175
User’s Manual U14359EJ4V0UM
5.3.7 Self-refresh control function
When transferring to the IDLE or software STOP mode, or if the SELFREF signal becomes active, the DRAM
controller generates the CBR self-refresh cycle.
Note that the RASn pulse width of DRAM must meet the specifications for DRAM to enable the self-refresh
operation (n = 1, 3, 4, 6).
Cautions 1. When the transition to the self-refresh cycle is caused by SELFREF signal input, releasing
the self-refresh cycle is only possible by inputting an inactive level to the SELFREF pin.
2. The internal ROM and internal RAM can be accessed even in the self-refresh cycle.
However, access to a peripheral I/O register or external device is held pending until the self-
refresh cycle is cleared.
To release the self-refresh cycle, use one of the three methods below.
(1) Release by NMI input
(a) In the case of self-refresh cycle in IDLE mode
To release the self-refresh cycle, make the RASn, LCAS, and UCAS signals inactive (high level)
immediately.
(b) In the case of self-refresh cycle in software STOP mode
To release the self-refresh cycle, make the RASn, LCAS, and UCAS signals inactive (high level) after
stabilizing oscillation.
(2) Release by INTP0n0 and INTP0n1 inputs (n = 0 to 3)
(a) In the case of self-refresh cycle in IDLE mode
To release the self-refresh cycle, make the RASn, LCAS, and UCAS signals inactive (high level)
immediately.
(b) In the case of self-refresh cycle in software STOP mode
To release the self-refresh cycle, make the RASn, LCAS, and UCAS signals inactive (high level) after
stabilizing oscillation.
(3) Release by RESET input
