User’s Manual U14359EJ4V0UM
20
LIST OF FIGURES (1/5)
Figure No.
Title
Page
3-1
CPU Address Space.......................................................................................................................................72
3-2
Images on Address Space..............................................................................................................................73
3-3
Memory Map (
µ
PD703103A, 703105A)..........................................................................................................75
3-4
Memory Map (
µ
PD703106A, 703107A, 70F3107A) .......................................................................................76
3-5
Internal ROM Area in Single-Chip Mode 1......................................................................................................79
3-6
Recommended Memory Map..........................................................................................................................84
4-1
Example When CSC0 Register Is Set to 0703H ...........................................................................................100
4-2
Big Endian Addresses Within Word ..............................................................................................................106
4-3
Little Endian Addresses Within Word............................................................................................................106
4-4
Timing Example of Access to SRAM, External ROM, and External I/O (Read
→
Write) ..............................123
4-5
Example of Wait Insertion .............................................................................................................................124
5-1
Examples of Connection to SRAM................................................................................................................142
5-2
SRAM, External ROM, External I/O Access Timing......................................................................................144
5-3
Examples of Connection to Page ROM ........................................................................................................151
5-4
On-Page/Off-Page Judgment During Page ROM Connection ......................................................................152
5-5
Page ROM Access Timing............................................................................................................................155
5-6
Examples of Connection to DRAM ...............................................................................................................160
5-7
Row Address/Column Address Output .........................................................................................................161
5-8
EDO DRAM Access Timing ..........................................................................................................................165
5-9
CBR Refresh Timing.....................................................................................................................................174
5-10
Self-Refresh Timing (DRAM) ........................................................................................................................176
5-11
Example of Connection to SDRAM...............................................................................................................177
5-12
Row Address/Column Address Output .........................................................................................................178
5-13
State Transition of SDRAM Access ..............................................................................................................182
5-14
SDRAM Single Read Cycle ..........................................................................................................................184
5-15
SDRAM Single Write Cycle...........................................................................................................................188
5-16
SDRAM Access Timing ................................................................................................................................192
5-17
Auto-Refresh Cycle.......................................................................................................................................199
5-18
CBR Refresh Timing (SDRAM).....................................................................................................................200
5-19
Self-Refresh Timing (SDRAM)......................................................................................................................202
5-20
SDRAM Mode Register Setting Cycle ..........................................................................................................204
5-21
SDRAM Register Write Operation Timing.....................................................................................................205
6-1
DMAC Bus Cycle State Transition ................................................................................................................223
6-2
Single Transfer Example 1 ...........................................................................................................................224
6-3
Single Transfer Example 2 ...........................................................................................................................224
