NEC V850E/MA1, User Manual

Page: 194 / 567

CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
Figure 5-16. SDRAM Access Timing (3/4)
(c) Write timing (16-bit bus width word access, bank change, BCW = 1, latency = 2)
SDCLK (output)
Note (output)
A11 (output)
A0 to A10 (output)
BCYST (output)
Bank address (output)
SDRAS (output)
SDCAS (output)
CSn (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
SDCKE (Output)
D0 to D15 (I/O)
Add. Add. Add. Add. Add. Add.
Add. Add. Add.
Col. Add. Row Col. Row Col. Col. Col. Col.
Data Data Data Data
H
TW TACT TWR TWR TWPRE
BCW
Bank A write
TWE TACT TW TWR TWR
BCW
Bank B write
TWPRE TWE TW TW TWE TWR TWR TWPRE
Bank B write
Bank A write
command
Bank A write
command
Bank B write
command
Bank A active
command
Bank B active
command
Bank B write
command
Bank B write
command
Bank B write
command
Bank A precharge
command
Add. Bnk. Add. Bnk. Bnk. Add.
Add. Add. Add.
Add.
Add.
Row Add. Row Add.
Data Data
When write-accessing the page
that includes bank B, which was
accessed by the previous write
access.
Note Addresses other than the bank address, A11, and A0 to A10.
Remarks 1. The circle
{
indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
4. Add.: Address
Bnk.: Bank address
Col.: Column address
Row: Row address