6
User’s Manual U14359EJ4V0UM
Major Revisions in This Edition (1/3)
Page
Description
Throughout
•
Deletion of the following products:
µ
PD703103, 703105, 703106, 703107, and 70F3107
•
Addition of the following product names:
µ
PD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A), 70F3107A, and 70F3107A(A)
p.30
Change of description in
1.4 Ordering Information
p.32
Change of pin configuration in
1.5 Pin Configuration (Top View) 161-pin plastic FBGA (13
××××
13)
p.38
Addition of
1.7 Differences Among Products
p.53
Modification of description in
2.3 (9) (b) (i) WAIT (Wait)
p.54
Addition of Caution to
2.3 (9) (b) (vii) SELFREF (Self-refresh request)
p.74
Modification of Caution in
3.4.3 (1) Program space
p.80
Change of description and addition of Caution in
3.4.5 (2) Internal RAM area
p.83
Deletion of description from
3.4.7 (1) Program space
p.92
Change of Bit Units for Manipulation in
3.4.8 Peripheral I/O registers DMA terminal count output
control register
p.94
Change of description in Table and addition of Remark to
3.4.10 System wait control register (VSWC)
p.96
Change of description in
4.2.1 Pin status during internal ROM, internal RAM, and peripheral I/O
access
p.98
Addition of Caution to
4.3.1 Chip select control function
p.102
Addition of description to
4.4.1 (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1)
p.103
Change of description in
4.5.1 Number of access clocks
p.104
Addition of description to
4.5.2 (1) Bus size configuration register (BSC)
p.105
Addition of Caution to
4.5.3 (1) Endian configuration register (BEC)
p.121
Addition of Caution to
4.6.1 (2) Address setup wait control register (ASC)
p.122
Change of description in and Addition of Caution to
4.6.1 (3) Bus cycle period control register (BCP)
p.162
Addition of description to
5.3.4 DRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6)
p.180
Change of description to LTM2n to LTM0n bits = 00x in
5.4.4 SDRAM configuration registers 1, 3, 4, 6
(SCR1, SCR3, SCR4, SCR6)
pp.194, 195
Change of description in
Figure 5-16 SDRAM Access Timing
p.215
Addition of Caution to
6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
p.217
Change of description in and addition of reserved word < > of device file to bits 3 to 0 to
6.3.8 DMA
terminal count output control register (DTOC)
p.218
Addition of Caution to
6.3.9 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
p.224
Addition of description and Figure to
6.5.1 Single transfer mode
p.227
Addition of description to
6.5.3 Block transfer mode
p.256
Addition of Caution to
6.8 DMA Channel Priorities
p.262
Addition of description to
6.16 One-Time Transfer During Single Transfer via DMARQ0 to DMARQ3
Signals
p.263
Addition of
6.17 (5) DMA start factors
p.264
Deletion of description from
Chapter 7 Interrupt/Exception Processing Function
p.269
Change of description in
Figure 7-2 Acknowledging Non-Maskable Interrupt Request
