NEC V850E/MA1, User Manual

Page: 303 / 567

CHAPTER 9 CLOCK GENERATION FUNCTION
303
User’s Manual U14359EJ4V0UM
9.3.4 Clock control register (CKC)
The clock control register is an 8-bit register that controls the internal system clock (f
XX
) in PLL mode. It can be
written to only by a specific sequence combination so that it cannot easily be overwritten by mistake due to an
inadvertent program loop.
This register can be read or written in 8-bit units.
Caution Do not change bits CKDIV2 to CKDIV0 in direct mode.
7 6 5 4 3 2 1 0 Address After reset
CKC 0 0 TBCS CESEL 0 CKDIV2 CKDIV1 CKDIV0 FFFFF822H 00H
Bit position Bit name Function
5 TBCS Time Base Count Select
Selects the time base counter clock.
0: f
X
/2
8
1: f
X
/2
9
For details, see 9.6.2 Time base counter (TBC) .
4 CESEL Crystal/External Select
Specifies the functions of the X1 and X2 pins.
0: A resonator is connected to the X1 and X2 pins
1: An external clock is connected to the X1 pin
When CESEL = 1, the oscillator feedback loop is disconnected to prevent current
leak in software STOP mode.
Clock Divide
Sets the internal system clock (f
XX
) when PLL mode is used.
CKDIV2 CKDIV1 CKDIV0 Internal system clock (f
XX
)
0 0 0 f
X
0 0 1 2.5 × f
X
0 1 1 5 × f
X
1 1 1 10 × f
X
Other than above Setting prohibited
2 to 0 CKDIV2 to
CKDIV0
To change the internal system clock frequency in the middle of an operation, be
sure to set it to f
X
first, and then change the frequency as desired.
Example Clock generator settings
CKC Register Operation
Mode
CKSEL Pin
CKDIV2 CKDIV0 CKDIV0
Input Clock (f
X
) Internal System
Clock (f
XX
)
Direct mode High-level input 0 0 0 16 MHz 8 MHz
0 0 0 5 MHz 5 MHz
0 0 1 5 MHz 12.5 MHz
0 1 1 5 MHz 25 MHz
PLL mode Low-level input
1 1 1 5 MHz 50 MHz
Other than above Setting prohibited Setting prohibited