CHAPTER 9 CLOCK GENERATION FUNCTION
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User’s Manual U14359EJ4V0UM
9.6
Securing Oscillation Stabilization Time
9.6.1 Oscillation stabilization time security specification
Two specification methods can be used to secure the time from when software STOP mode is released until the
stopped oscillator stabilizes.
(1) Securing the time using an on-chip time base counter
Software STOP mode is released when a valid edge is input to the NMI pin or a maskable interrupt request is
input (INTP1nn). If oscillation is started by inputting an active edge to the pin, the time base counter (TBC)
starts counting, and the time required for the clock output from the oscillation circuit to be stabilized is
secured within that count time (n = 0 to 3).
Oscillation stabilization time = TBC counting time
After a fixed time, internal system clock output begins, and processing branches to the NMI interrupt or
maskable interrupt (INTP1nn) handler address.
Oscillation waveform
(X2)
Set software STOP mode
Oscillator is stopped
CLKOUT (output)
Internal main clock
STOP state
NMI (input)
Note
Time base counter's
counting time
Note
Valid edge: When specified as the rising edge.
The NMI pin should usually be set to an inactive level (for example, high level when the valid edge is
specified as the falling edge) in advance.
Software STOP mode is immediately released if STOP mode is set by NMI valid edge input or maskable
interrupt request input (INTP1nn) before the CPU acknowledges the interrupt.
If direct mode or external clock connection mode (CESEL bit of CKC register = 1) is used, program execution
begins after the count time of the time base counter has elapsed.
Also, even if PLL mode and resonator connection mode (CESEL bit of CKC register = 0) are used, program
execution begins after the oscillation stabilization time is secured according to the time base counter.
