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CHAPTER 1 INTRODUCTION
36
User’s Manual U14359EJ4V0UM
1.6.2 On-chip units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic
logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits
×
16 bits
→
32 bits or 32 bits
×
32 bits
→
64
bits) and a barrel shifter (32 bits), help accelerate processing of complex instructions.
(2) Bus control unit (BCU)
The BCU starts the required external bus cycle based on the physical address obtained by the CPU. When
an instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the
BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is
stored in an instruction queue in the CPU.
The BCU controls a DRAM controller (DRAMC), page ROM controller (ROMC), and DMA controller (DMAC)
and performs external memory access and DMA transfer.
(a) DRAM controller (DRAMC)
(i)
SDRAM
The DRAM controller generates the SDRAS, SDCAS, UDQM, and LDQM signals and performs
access control for SDRAM.
CAS latency 2 and 3 are supported, and the burst length is fixed to 1.
A refresh function that supports the CBR refresh cycle and a dynamic self-refresh function based on
an external input are also available.
(ii) EDO DRAM
The DRAM controller generates the RAS, UCAS, and LCAS signals (2CAS control) and performs
access control for EDO DRAM.
EDO DRAM is supported, and there are two types of access: normal access (off page) and page
access (on page).
A refresh function that supports the CBR refresh cycle and a dynamic self-refresh function based on
an external input are also available.
(b) Page ROM controller (ROMC)
This controller supports accessing ROM that includes the page access function.
It performs address comparisons with the immediately preceding bus cycle and executes wait control for
normal access (off-page)/page access (on-page). It can handle page widths of 8 to 128 bytes.
(c) DMA controller (DMAC)
This controller controls data transfer between memory and I/O instead of the CPU.
There are two address modes: flyby (1-cycle) transfer, and 2-cycle transfer. There are three bus modes,
single transfer, single step transfer, and block transfer.