CHAPTER 2 PIN FUNCTIONS
55
User’s Manual U14359EJ4V0UM
(10) PCT0, PCT1, PCT4 to PCT7 (Port CT) ··· 3-state I/O
PCT0, PCT1, PCT4 to PCT7 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in the control mode, these pins operate as control signal outputs for when
memory is expanded externally.
The operation mode can be set to port or control mode in 1-bit units, specified by the port CT mode control
register (PMCCT).
(a) Port mode
PCT0, PCT1, PCT4 to PCT7 can be set to input or output in 1-bit units using the port CT mode register
(PMCT).
(b) Control mode
PCT0, PCT1, PCT4 to PCT7 can be set to port/control mode in 1-bit units using the PMCCT register.
(i)
LCAS (Lower column address strobe) ··· 3-state output
This is the column address strobe signal for DRAM and the strobe signal for the CBR refresh cycle.
For the data bus, the lower byte is valid.
(ii) UCAS (Upper column address strobe) ··· 3-state output
This is the column address strobe signal for DRAM and the strobe signal for the CBR refresh cycle.
For the data bus, the higher byte is valid.
(iii) LWR (Lower byte write strobe) ··· 3-state output
This strobe signal shows whether the bus cycle currently being executed is a write cycle for the
SRAM, external ROM, or external peripheral I/O area.
For the data bus, the lower byte becomes valid. If the bus cycle is a lower memory write, it becomes
active at the falling edge of the CLKOUT signal in the T1 state and becomes inactive at the falling
edge of the CLKOUT signal in the T2 state.
(iv) UWR (Upper byte write strobe) ··· 3-state output
This strobe signal shows whether the bus cycle currently being executed is a write cycle for the
SRAM, external ROM, or external peripheral I/O area.
For the data bus, the higher byte becomes valid. If the bus cycle is a higher memory write, it
becomes active at the falling edge of the CLKOUT signal in the T1 state and becomes inactive at the
falling edge of the CLKOUT signal in the T2 state.
(v) LDQM (Lower DQ mask enable) ··· 3-state output
This is a control signal for the data bus to SDRAM. For the data bus, the lower byte is valid. This
signal carries out SDRAM output disable control during a read operation, and SDRAM byte mask
control during a write operation.
(vi) UDQM (Upper DQ mask enable) ··· 3-state output
This is a control signal for the data bus to SDRAM. For the data bus, the higher byte is valid. This
signal carries out SDRAM output disable control during a read operation, and SDRAM byte mask
control during a write operation.
