NEC V850E/MA1, User Manual

Page: 365 / 567

CHAPTER 11 SERIAL INTERFACE FUNCTION
User’s Manual U14359EJ4V0UM
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(2) Asynchronous serial interface status registers 0 to 2 (ASIS0 to ASIS2)
These registers, which consist of 3-bit error flags (PEn, FEn, and OVEn), indicate the error status when
UARTn reception is completed (n = 0 to 2).
The status flag, which indicates a reception error, always indicates the status of the error that occurred most
recently. That is, if the same error occurred several times before the receive data was read, this flag would
hold only the status of the error that occurred last.
The ASISn register is cleared to 00H by a read operation. When a reception error occurs, the receive buffer
(RXBn) should be read after the ASISn register is read.
These registers are read-only in 8-bit units.
Caution When the UARTCAEn bit or RXEn bit of the ASIMn register is set to 0, or when the ASISn
register is read, the PEn, FEn, and OVEn bits of the ASISn register are cleared (0).
7 6 5 4 3 2 1 0 Address After reset
ASIS0 0 0 0 0 0 PE0 FE0 OVE0 FFFFFA03H 00H
ASIS1 0 0 0 0 0 PE1 FE1 OVE1 FFFFFA13H 00H
ASIS2 0 0 0 0 0 PE2 FE2 OVE2 FFFFFA23H 00H
Bit position Bit name Function
2
PEn
(n = 0 to 2)
Parity Error
This is a status flag that indicates a parity error.
0: When the UARTCAEn and RXEn bits of the ASIMn register are cleared to 0
or when the ASISn register is read
1: When reception was completed, the transmit data parity did not match the
parity bit
Caution The operation of the PEn bit differs according to the settings of
the PSn1 and PSn0 bits of the ASIMn register.
1 FEn
(n = 0 to 2)
Framing Error
This is a status flag that indicates a framing error.
0: When the UARTCAEn and RXEn bits of the ASIMn register are cleared to 0
or when the ASISn register is read
1: When reception was completed, no stop bit was detected
Caution For receive data stop bits, only the first bit is checked regardless
of the stop bit length.
0 OVEn
(n = 0 to 2)
Overrun Error
This is a status flag that indicates an overrun error.
0: When the UARTCAEn and RXEn bits of the ASIMn register are cleared to 0
or when the ASISn register is read
1: UARTn completed the next receive operation before reading the RXBn
receive data.
Caution When an overrun error occurs, the next receive data value is not
written to the RXBn register and the data is discarded.