NEC V850E/MA1, User Manual

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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
255
User’s Manual U14359EJ4V0UM
6.7 Transfer Object
6.7.1 Transfer type and transfer object
Table 6-1 lists the relationships between transfer type and transfer object. The mark “
√
” means “transfer possible”,
and the mark “
−
” means “transfer impossible”.
Table 6-1. Relationship Between Transfer Type and Transfer Object
Destination
2-Cycle Transfer Flyby Transfer
Internal
ROM
On-chip
Peripheral
I/O
External
I/O
Internal
RAM
External
Memory
Internal
ROM
On-chip
Peripheral
I/O
External
I/O
Internal
RAM
External
Memory
On-chip
peripheral I/O
− √ √ √ √ − − − − −
External I/O
− √ √ √ √ − − − − √
Note
Internal RAM
− √ √ − √ − − − − −
External
memory
− √ √ √ √ − − √
Note
− −
S
ourc
e
Internal ROM
− − − − × − − − − −
Note In the case of flyby transfer, data cannot be transferred to/from SDRAM.
Cautions 1. The operation is not guaranteed for combinations of transfer destination and source marked
with “
−−−−
” in Table 6-1.
2. In the case of flyby transfer, make the data bus width the same for the source and
destination.
3. Addresses between 3FFF000H and 3FFFFFFH cannot be specified for the source and
destination address of DMA transfer. Be sure to specify an address between FFFF000H and
FFFFFFFH.
Remarks 1. During 2-cycle DMA transfer, if the data bus width of the transfer source and that of the transfer
destination are different, the operation becomes as follows.
<16-bit transfer>
•
Transfer from a 16-bit bus to an 8-bit bus
A read cycle (16 bits) is generated and then a write cycle (8 bits) is generated twice consecutively.
•
Transfer from an 8-bit bus to a 16-bit bus
A read cycle (8 bits) is generated twice consecutively and then a write cycle (16 bits) is generated.
<8-bit transfer>
•
Transfer from 16-bit bus to 8-bit bus
A read cycle (the higher 8 bits go into a high-impedance state) is generated and then a write cycle
(8 bits) is generated.
•
Transfer from 8-bit bus to 16-bit bus
A read cycle (8 bits) is generated and then a write cycle is generated (the higher 8 bits go into a
high-impedance state). Data is written in the order from lower bits to higher bits to the transfer
destination in the case of little endian and in reverse order in the case of big endian.
2. Transfer between the little endian area and the big endian area is possible.