CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U14359EJ4V0UM
6.5.3 Block transfer mode
In the block transfer mode, once transfer starts, the DMAC continues the transfer operation without releasing the
bus until a terminal count occurs. No other DMA requests are acknowledged during block transfer.
After the block transfer ends and the DMAC releases the bus, another DMA transfer can be acknowledged. The
bus cycle of the CPU is not inserted during block transfer, but bus hold and refresh cycles are inserted in between
DMA transfer operations.
The following shows an example of block transfer in which a higher priority DMA request is issued. DMA channels
2 and 3 are in the block transfer mode.
Figure 6-8. Block Transfer Example
CPU CPU CPU DMA3
DMA3
DMA3
DMA3
DMA3
DMA3
DMA3
DMA3 CPU DMA2
DMA2
DMA2
DMA2
DMA2
DMA channel 3
terminal count
The bus is always
released.
DMARQ3
(input)
DMARQ2
(input)
