NEC V850E/MA1, User Manual

Page: 192 / 567

CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
192
User’s Manual U14359EJ4V0UM
Figure 5-16. SDRAM Access Timing (1/4)
(a) Read timing (16-bit bus width word access, page change, BCW = 2, latency = 2)
Data Data Data Data
TW TBCW TACT TBCW TREAD TACT TLATE TREAD TLATE TREAD TREAD TLATE TLATE TBCW TW TPREC
Add. Add.
Add. Bnk. Add. Bnk. Add. Bnk.
Row Add. Col.
Col. Add.
Row
Add.
SDCLK (output)
Note (output)
A11 (output)
A0 to A10 (output)
BCYST (output)
Bank address (output)
SDRAS (output)
SDCAS (output)
CSn (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
SDCKE (output)
D0 to D15 (I/O)
H
BCW BCW BCW
Bank A read
command
Bank A read
command
Bank A read
command
(On-page)
Bank A read
command
(On-page)
Bank A precharge
command
(Page change)
Bank A active
command
Bank A active
command
Add. Add.
Add. Row Add. Add. Row
Add. Add.
Col.
Col.
Note Addresses other than the bank address, A11, and A0 to A10.
Remarks 1. The circle
{
indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
4. Add.: Address
Bnk.: Bank address
Col.: Column address
Row: Row address