CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
232
User’s Manual U14359EJ4V0UM
Figure 6-11. Timing of 2-Cycle DMA Transfer (SRAM
→
→
→
→
EDO DRAM) (1/3)
(a) Single transfer mode
CLKOUT (output)
DMARQx (input)
DMAAKx (output)
TCx (output)
Address (output)
Internal DMA
request signal
BCYST (output)
LCAS (output)
UCAS (output)
RASm (output) of
DRAM area
CSn (output)
of other area
CSn (output) of
SRAM area
RD (output)
OE (output)
WE (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Address
Row
Col.
Col.
Data
TI
TI
TI
TI
TO
T1R
T1W T2W T2W
T2R
TI
TI
T1
T2
T1
TI
TI
T1
TI
T2
TO
T2
T1
T2
TRPW
Note 2
Note 2
T1W
TCPW
Note 3
Note 4
T2W
TB
T2
T1
T2
TE
TW
TI
TW
Data
Data
Data
Address
TE
TI
T1
T1R
T1
T2R
T2
Data
Data
Data
Data
Note 1
Note 1
Notes 1.
This idle state (TI) is independent of the BCC register setting.
2.
TRPW and TCPW are always inserted for one or more cycles.
3.
When a bus cycle accessing another CS space or a read cycle accessing the same CS space
follows this write cycle.
4.
In the case of the RAS hold mode
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
4.
Col.: Column address
Row: Row address
