CHAPTER 9 CLOCK GENERATION FUNCTION
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User’s Manual U14359EJ4V0UM
9.3
Input Clock Selection
The clock generator consists of an oscillator and a PLL synthesizer. For example, connecting a 5.0 MHz crystal
resonator or ceramic resonator to pins X1 and X2 enables a 50 MHz internal system clock (f
XX
) to be generated when
multiplied by 10.
Also, an external clock can be input directly to the oscillator. In this case, the clock signal should be input only to
the X1 pin (the X2 pin should be left open).
Two basic operation modes are provided for the clock generator. These are PLL mode and direct mode. The
operation mode is selected by the CKSEL pin. The input to this pin is latched on reset.
CKSEL
Operating Mode
0
PLL mode
1
Direct mode
Caution
The input level for the CKSEL pin must be fixed. If it is switched during operation, malfunction
may occur.
9.3.1 Direct mode
In direct mode, an external clock with twice the frequency of the internal system clock is input. The maximum
frequency that can be input in direct mode is 50 MHz. The V850E/MA1 is mainly used in application systems in which
it is operated at relatively low frequencies.
Caution
In direct mode, an external clock must be input (an external resonator should not be
connected).
