CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U14359EJ4V0UM
(10) T1FH state
The basic flyby transfer state, this state corresponds to the transfer execution cycle.
After entering the T1FH state, the bus enters the T2FH state.
(11) T1FHI state
The T1FHI state corresponds to the last state of a flyby transfer, during which the end of transfer is waited
for.
After entering the T1FHI state, the bus is released and enters the TE state.
(12) T2FH state
The T2FH state is the state during which it is judged whether flyby transfer is to be continued or not.
If the next transfer is executed in the block transfer mode, the bus enters the T1FH state after the T2FH
state.
Under other conditions, the bus enters the T1FHI state when a wait is issued. If no wait is issued, the bus is
released and enters the TE state.
(13) TE state
The TE state corresponds to DMA transfer completion. The DMAC generates the internal DMA transfer
completion signal (TCn) and various internal signals are initialized (n = 0 to 3). After entering the TE state,
the bus invariably enters the TI state.
