CHAPTER 4 BUS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
4.4.1 Bus cycle type configuration registers 0, 1 (BCT0, BCT1)
(1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1)
These registers can be read/written in 16-bit units.
Be sure to set bits 14, 10, 9, 6, 2, and 1 to 0. If they are set to 1, the operation is not guaranteed.
Caution
Write to the BCT0 and BCT1 registers after reset, and then do not change the set value.
Also, do not access an external memory area other than the one for this initialization
routine until the initial setting of the BCT0 and BCT1 registers is complete. However, it is
possible to access external memory areas whose initialization settings are complete.
15
ME3
BCT0
CSn signal
Address
FFFFF480H
After reset
8888H
14
0
13
BT31
12
BT30
11
ME2
10
0
9
0
8
BT20
7
ME1
6
0
5
BT11
4
BT10
3
ME0
2
0
1
0
0
BT00
CS3
CS2
CS1
CS0
15
ME7
BCT1
CSn signal
Address
FFFFF482H
After reset
8888H
14
0
13
0
12
BT70
11
ME6
10
0
9
BT61
8
BT60
7
ME5
6
0
5
0
4
BT50
3
ME4
2
0
1
BT41
0
BT40
CS7
CS6
CS5
CS4
Bit position
Bit name
Function
Memory Controller Enable
Sets memory controller operation enable for each chip select.
MEn
Memory controller operation enable
0
Operation disabled
1
Operation enabled
15, 11, 7, 3
(BCT0),
15, 11, 7, 3
(BCT1)
MEn
(n = 0 to 7)
Bus Cycle Type
Specifies the device to be connected to the CSn signal.
BTn0
External device connected to CSn signal
0
SRAM, external I/O
1
Page ROM
8, 0 (BCT0),
12, 4 (BCT1)
BTn0
(n = 0, 2, 5, 7)
Bus Cycle Type
Specifies the device to be connected to the CSn signal.
BTn1
BTn0
External device connected to CSn signal
0
0
SRAM, external I/O
0
1
Page ROM
1
0
EDO DRAM
1
1
SDRAM
13, 12, 5, 4
(BCT0),
9, 8, 1, 0
(BCT1)
BTn1, BTn0
(n = 1, 3, 4, 6)
