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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
231
User’s Manual U14359EJ4V0UM
Figure 6-10. Timing of 2-Cycle DMA Transfer (External I/O
→
→
→
→
SRAM)
(a) Single-step transfer mode
TI
TI
TI
TI
TI
Note 1
TO
T1R
T1
T2R
T2
T1W
T1
T2W
T2
T1R
T1
T2R
TW
T2R
T2
TI
Note 1
T2W
TW
T1W
T1
T2W
T2
TI
TI
TI
TO
CSn (output) of
SRAM area
D0 to D15 (I/O)
A0 to A25 (output)
Internal DMA
request signal
DMARQx (input)
CLKOUT (output)
BCYST (output)
TCx (output)
CSm (output) of
external I/O area
OE (output)
RD (output)
IORD (output)
Note 2
IOWR (output)
Note 2
WAIT (input)
WE (output)
Data
Data
H
H
DMAAKx (output)
LWR/LCAS (output)
UWR/UCAS (output)
Address
Address
Address
Address
Data
Data
Notes 1.
This idle state (TI) is independent of the BCC register setting.
2.
When the IOEN bit of the BCP register is set to 1.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 0 to 7, m = 0 to 7, x = 0 to 3 (n
≠
m)