CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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User’s Manual U14359EJ4V0UM
(3) Condition 3
Condition
Instruction fetch from an external memory in 8-bit data bus width
Execution of a bit manipulation instruction (SET1, CLR1, or NOT1)
Response time
Tinst
×
4 + Tdata
×
2 + Tref
DMAAKn (output)
D0 to D15 (I/O)
DMARQn (input)
DMA cycle
Refresh
Data write
Data read
Fetch (4/4)
Fetch (3/4)
Fetch (2/4)
Fetch (1/4)
Remarks 1.
Tinst:
Number of clocks per bus cycle during instruction fetch
Tdata: Number of clocks per bus cycle during data access
Tref:
Number of clocks per refresh cycle
2.
n = 0 to 3
6.16 One-Time Transfer During Single Transfer via DMARQ0 to DMARQ3 Signals
The DMARQn signal is sampled at the rising edge of the third clock after the cycle of DMA transfer in the single-
transfer mode has been completed. To perform transfer only one time when single transfer is executed for an
external memory via the DMARQn signal, the DMARQn signal must be made inactive within 3 clocks from when the
DMAAKn signal becomes inactive (n = 0 to 3).
Figure 6-24. Time to Perform Single Transfer One Time
DMAAKn (output)
CLKOUT (output)
DMARQn (input)
DMA request sampling period
Period without sampling DMA request
DMA transfer cycle
In the single transfer mode, the next
DMA transfer does not start if the DMARQn
signal rises within three clocks.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
n = 0 to 3