CHAPTER 12 A/D CONVERTER
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User’s Manual U14359EJ4V0UM
12.6 Operation in Timer Trigger Mode
Conversion timings for up to four-channel analog inputs (ANI0 to ANI3) can be set for the A/D converter using the
interrupt signal output from the TMC compare register.
Two 16-bit timers (TMC0, TMC1) and four capture/compare registers (CCC00, CCC01, CCC10, CC11) are used
for the timer to specify the analog conversion trigger.
The following two modes are provided according to the value set in the TMCC01 or TMCC11 register.
(1) 1-shot mode
To use the 1-shot mode, set the OSTn bit of the TMCCn1 register (overflow stop mode) to 1 (n = 0, 1).
When TMC overflows, 0000H is held, and counter operation stops. Thereafter, TMCn does not output the
match interrupt signal (A/D conversion trigger) of the compare register, and the A/D converter enters the A/D
conversion standby state. The TMCn count operation restarts when the TMCCEn bit of the TMCCn0 register
is set to 1. The 1-shot mode is used when the A/D conversion cycle is longer than the TMC cycle. (n = 0, 1).
(2) Loop mode
To use the loop mode, set the OST bit (free-running mode) of the TMCCn1 register to 0 (n = 0, 1).
When TMCn overflows, it starts counting from 0000H again, and the match interrupt signal (A/D conversion
trigger) of the compare register is repeatedly output. A/D conversion is also repeated.