CHAPTER 1 INTRODUCTION
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User’s Manual U14359EJ4V0UM
1.2
Features
{
Number of instructions:
83
{
Minimum instruction execution time:
20 ns (at internal 50 MHz operation)
{
General-purpose registers:
32 bits
×
32
{
Instruction set:
V850E1 CPU
Signed multiplication (16 bits
×
16 bits
→
32 bits or 32 bits
×
32 bits
→
64 bits): 1 to 2 clocks
Saturated operation instructions (with overflow/underflow detection
function)
32-bit shift instructions: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Signed load instructions
{
Memory space:
256 MB linear address space (common program/data use)
Chip select output function: 8 spaces
Memory block division function: 2, 4, 8 MB/block
Programmable wait function
Idle state insertion function
{
External bus interface:
16-bit data bus (address/data separated)
16-/8-bit bus sizing function
Bus hold function
External wait function
Address setup wait function
Endian control function
Part Number
Internal ROM
Internal RAM
µ
PD703103A
None
4 KB
µ
PD703105A
128 KB (Mask ROM)
4 KB
µ
PD703106A
128 KB (Mask ROM)
10 KB
µ
PD703107A
256 KB (Mask ROM)
10 KB
{
Internal memory
µ
PD70F3107A
256 KB (Flash memory)
10 KB
{
Interrupts/exceptions:
External interrupts: 25 (including NMI)
Internal interrupts: 33 sources
Exceptions:
1 source
Eight levels of priorities can be set.
{
Memory access controller
DRAM controller (compatible with EDO DRAM and SDRAM)
Page ROM controller
