CHAPTER 2 PIN FUNCTIONS
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User’s Manual U14359EJ4V0UM
(iii) BUSCLK (Bus clock output) ··· output
This pin outputs a bus clock only in the bus cycle when the external bus cycle period is set to two
times that of the normal. The bus clock operates at the operating frequency of 1/2 the internal
system clock by setting the bus cycle period control register (BCP). To execute BUSCLK output, set
the port CM mode control register (PMCCM) and the port CM function control register (PFCCM).
(iv) HLDAK (Hold acknowledge) ··· output
In this mode, this pin is the acknowledge signal output pin that indicates the high impedance status
for the address bus, data bus, and control bus when the V850E/MA1 receives a bus hold request.
While this signal is active, the impedance of the address bus, data bus and control bus becomes
high and the bus mastership is transferred to the external bus master.
(v) HLDRQ (Hold request) ··· input
In this mode, this pin is the input pin through which an external device requests the V850E/MA1 to
release the address bus, data bus, and control bus. The HLDRQ signal can be input asynchronously
to the CLKOUT signal. When this pin is active, the address bus, data bus, and control bus are set to
the high impedance status. This occurs either when the V850E/MA1 completes execution of the
current bus cycle or immediately if no bus cycle is being executed, then the HLDAK signal is set as
active and the bus is released.
In order to make the bus hold state secure, keep the HLDRQ signal active until the HLDAK signal is
output.
(vi) REFRQ (Refresh request) ··· output
This is the refresh request signal for DRAM.
In cases when the address is decoded by an external circuit to increase the connected DRAM, or in
cases when external SIMM’s are connected, this signal is used for RAS control during the refresh
cycle.
This signal becomes active during the refresh cycle. Also, during bus hold, it becomes active when a
refresh request is generated and informs the external bus master that a refresh request was
generated.
(vii) SELFREF (Self-refresh request) ··· input
This is a self-refresh request signal input for DRAM.
The internal ROM and internal RAM can be accessed even in the self-refresh cycle. However,
access to a peripheral I/O register or external device is held pending until the self-refresh cycle is
cancelled.
Caution In ROMless modes 0 and 1, and single-chip mode 1, input to the SELFREF pin
becomes valid immediately after the reset signal has been cleared. Consequently,
if a high level is input to the SELFREF pin by an external pull-up resistor, self
refreshing is started. Note that, at this time, the normal instruction fetch cycle does
not occur.
