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CHAPTER 4 BUS CONTROL FUNCTION
123
User’s Manual U14359EJ4V0UM
Figure 4-4. Timing Example of Access to SRAM, External ROM, and External I/O (Read
→
→
→
→
Write)
T1
T2
Data
Data
WAIT (input)
D0 to D15 (I/O)
IOWR (output)
LWR/LCAS (output)
IORD (output)
Note
UWR/UCAS (output)
WE (output)
OE (output)
RD (output)
BCYST (output)
A0 to A25 (output)
Internal system
clock
T2
T1
CSn/RASm (output)
LBE (output)
UBE (output)
BUSCLK (output)
Address
Address
Note
When the IOEN bit of the BCP register is set to 1.
Remarks 1.
The
circle
{
indicates the sampling timing.
2.
The broken lines indicate the high-impedance state.
3.
n = 0 to 7, m = 1, 3, 4, 6