NEC V850E/MA1, User Manual

Page: 212 / 567

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
212
User’s Manual U14359EJ4V0UM
6.3.3 DMA byte count registers 0 to 3 (DBC0 to DBC3)
These 16-bit registers are used to set the byte transfer count for DMA channel n (n = 0 to 3). They store the
remaining transfer count during DMA transfer.
Since these registers are configured as 2-stage FIFO buffer registers, a new DMA byte transfer count for DMA
transfer can be specified during DMA transfer. (Refer to 6.9 Next Address Setting Function .)
These registers are decremented by 1 for each transfer, and transfer ends when a borrow occurs.
These registers can be read/written in 16-bit units.
Remark If the DBCn register is read during DMA transfer after a terminal count has occurred without the
register being overwritten, the value set immediately before the DMA transfer will be read out (0000H
will not be read, even if DMA transfer has ended).
15
BC15 DBC0
Address
FFFFF0C0H
After reset
Undefined
14
BC14
13
BC13
12
BC12
11
BC11
10
BC10
9
BC9
8
BC8
7
BC7
6
BC6
5
BC5
4
BC4
3
BC3
2
BC2
1
BC1
0
BC0
BC15 DBC1
FFFFF0C2H Undefined
BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
BC15 DBC2
FFFFF0C4H Undefined
BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
BC15 DBC3 FFFFF0C6H Undefined BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
Bit position Bit name Function
Byte Count
Sets the byte transfer count and stores the remaining byte transfer count during
DMA transfer.
DBCn (n = 0 to 3) States
0000H
Byte transfer count 1 or remaining byte transfer count
0001H
Byte transfer count 2 or remaining byte transfer count
:
:
FFFFH
Byte transfer count 65,536 (2
16
) or remaining byte transfer
count
15 to 0 BC15 to BC0