![background image](http://html1.mh-extra.com/html/nec/v850e-ma1/v850e-ma1_user-manual_4538839013.webp)
User’s Manual U14359EJ4V0UM
13
4.1
Features..................................................................................................................................... 95
4.2
Bus Control Pins ...................................................................................................................... 95
4.2.1
Pin status during internal ROM, internal RAM, and peripheral I/O access................................... 96
4.3
Memory Block Function........................................................................................................... 97
4.3.1
Chip select control function .......................................................................................................... 98
4.4
Bus Cycle Type Control Function......................................................................................... 101
4.4.1
Bus cycle type configuration registers 0, 1 (BCT0, BCT1) ......................................................... 102
4.5
Bus Access ............................................................................................................................. 103
4.5.1
Number of access clocks ........................................................................................................... 103
4.5.2
Bus sizing function ..................................................................................................................... 104
4.5.3
Endian control function .............................................................................................................. 105
4.5.4
Big endian method usage restrictions in NEC development tools.............................................. 106
4.5.5
Bus width ................................................................................................................................... 108
4.6
Wait Function.......................................................................................................................... 119
4.6.1
Programmable wait function ...................................................................................................... 119
4.6.2
External wait function................................................................................................................. 124
4.6.3
Relationship between programmable wait and external wait ..................................................... 124
4.6.4
Bus cycles in which wait function is valid ................................................................................... 125
4.7
Idle State Insertion Function ................................................................................................. 126
4.8
Bus Hold Function.................................................................................................................. 127
4.8.1 Function
outline.......................................................................................................................... 127
4.8.2
Bus hold procedure.................................................................................................................... 128
4.8.3
Operation in power-save mode .................................................................................................. 128
4.8.4
Bus hold timing (SRAM)............................................................................................................. 129
4.8.5
Bus hold timing (EDO DRAM).................................................................................................... 131
4.8.6
Bus hold timing (SDRAM) .......................................................................................................... 135
4.9
Bus Priority Order .................................................................................................................. 139
4.10 Boundary Operation Conditions........................................................................................... 140
4.10.1 Program
space .......................................................................................................................... 140
4.10.2
Data space................................................................................................................................. 140
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION.................................................................. 141
5.1
SRAM, External ROM, External I/O Interface ....................................................................... 141
5.1.1
Features..................................................................................................................................... 141
5.1.2 SRAM
connection ...................................................................................................................... 142
5.1.3
SRAM, external ROM, external I/O access................................................................................ 144
5.2
Page ROM Controller (ROMC)............................................................................................... 150
5.2.1
Features..................................................................................................................................... 150
5.2.2
Page ROM connection............................................................................................................... 151
5.2.3 On-page/off-page
judgment ....................................................................................................... 152
5.2.4
Page ROM configuration register (PRC)....................................................................................154
5.2.5
Page ROM access ..................................................................................................................... 155
5.3
DRAM Controller (EDO DRAM) ............................................................................................. 159
5.3.1
Features..................................................................................................................................... 159
5.3.2
DRAM connection ...................................................................................................................... 160
5.3.3
Address multiplex function ......................................................................................................... 161