CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
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User’s Manual U14359EJ4V0UM
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Bit position
Bit name
Function
Address Shift Width On-page Control
This sets the address shift width during on-page judgment.
When the external data bus width is 8 bits: Set ASO1n, ASO0n = 00B
When the external data bus width is 16 bits: Set ASO1n, ASO0n = 01B
ASO1n
ASO0n
Address shift width
0
0
0 (data bus width: 8 bits)
0
1
1 (data bus width: 16 bits)
1
0
Setting prohibited
1
1
Setting prohibited
3, 2
ASO1n,
ASO0n
(n = 1, 3,
4, 6
DRAM Address Multiplex Width Control
This sets the address multiplex width (refer to
5.3.3 Address multiplex function
).
DAW1n
DAW0n
Address multiplex width
0
0
8 bits
0
1
9 bits
1
0
10 bits
1
1
11 bits
1, 0
DAW1n,
DAW0n
(n = 1, 3,
4, 6)
